100G MAC + PCS (100GBASE-R4/R10)

Block Diagram

Solution Type: IP Core

End Market: Computer & Storage, Military, Test & Measurement, Wireline

Evaluation Method: OpenCore Plus, Source Code

Technology: Interface Protocols: Ethernet

Arria Series: Arria 10, Arria 10 SoC

Stratix Series: Stratix V

Overview

The 100G Ethernet MAC and PCS is the industry leading solution for latency critical Ethernet applications such as data center Ethernet switches. The core is designed using advanced techniques leading to unmatched, ultra-low gate count utilization and amazing latency performances. The IP core supports full wire line speed with a 64-byte packet length. It also supports back-to-back or mixed length traffic, up to jumbo frame size, with no dropped packets.

Features

    Device Utilization and Performance

    Area (1): LUTs: 19,927 FFs: 16,374 BRAM: 0 Performances: Clock: 390.625MHz Timing margin: 15% (2) Latency: 92.2ns (round-trip latency MAC+PCS) (1): Resources utilization includes internal statistics counters (2): Timing margin is based on Altera Stratix-V mid-speed grade device

    Getting Started

    Note: Not available yet (planned as Arria-10 GT platforms become available) Complete Arria-10 reference design which will be including: - 100G MAC & PCS IP integrated with high-speed transceivers, clock and CPU interface - Software Command Line Interface (CLI) to configure and monitor statistics - Simple RTL test benches (optional Verification IP - UVM based) - Product documentation, register mapping

    IP Quality Metrics

    Basic
    Year IP was first released2016
    Latest version of Quartus supported15.1
    Altera Customer Use
    IP has been successfully implemented in production with at least one customerN
    Deliverables

    Customer deliverables include the following:

    • Design file (encrypted source code or post-synthesis netlist)
    • Simulation model for ModelSim Altera edition
    • Timing and/or layout constraints
    • Testbench or design example
    • Documentation with revision control
    • Readme file
    Y
    Any additional customer deliverables provided with IP
    Optional Verification IP
    Parameterization GUI allowing end user to configure IPN
    IP core is enabled for OpenCore Plus SupportY
    Source language
    Verilog
    Testbench languageVerilog
    Software drivers providedY
    Driver OS supportLinux
    Implementation
    User InterfaceOther: Custom data bus
    IP-XACT Metadata includedN
    Verification
    Simulators supportedMentor Graphics (Modelsim, Questa)
    Hardware validated N. Altera Board Name HiTech Global: HTG-S5-PCIE-A7
    Industry standard compliance testing performed
    N
    If No, is it planned?Y
    Interoperability
    IP has undergone interoperability testing
    N
    Interoperability reports available  N

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