40G MAC + PCS (40GBASE-R4)

Block Diagram

Solution Type: IP Core

End Market: Computer & Storage, Military, Test & Measurement, Wireless, Wireline

Evaluation Method: OpenCore Plus, Source Code

Technology: Interface Protocols: Ethernet

Arria Series: Arria 10, Arria 10 SoC

Stratix Series: Stratix V

Segments: 

Supported Device Family: 

Solution Type: 

Overview

The Ultra-Low Latency Ethernet MAC and PCS is the industry leading solution for latency critical Ethernet applications such as high-frequency trading and data center Ethernet switches. The core is designed using advanced techniques leading to unmatched, ultra-low gate count utilization and amazing latency performances. The IP core supports full wire line speed with a 64-byte packet length. It also supports back-to-back or mixed length traffic, up to jumbo frame size, with no dropped packets.

Features

  • Compliant with the IEEE 802.3-2012 High Speed Ethernet Standard
  • Highly optimized implementation resulting in ultra-low latency and very low gate count
  • Soft PCS logic (40GBASE-R4) interfacing to four (4) serial transceivers at 10.3125Gbps
  • Programmable Tx and Rx path VLAN detection
  • Configurable statistics vector and collector on transmit and receive MAC/PCS data

Device Utilization and Performance

Area (1): LUTs: 8,078 FF: 7,678 BRAM: 0 Performance: Clock: 312.5MHz Timing margin: 20% (2) Latency: 80.0ns (MAC + PCS round-trip) (1): Resources utilization includes internal statistics counters (2): Timing margin is based on Altera Stratix-V mid-speed grade device

Getting Started

Complete Stratix-V reference design available including: - 40G MAC & PCS IP integrated with high-speed transceivers, clock and CPU interface - Software Command Line Interface (CLI) to configure and monitor statistics - Simple RTL test benches (optional Verification IP - UVM based) - Product documentation, register mapping.

IP Quality Metrics

Basic
Year IP was first released2016
Latest version of Quartus supported15.1
Altera Customer Use
IP has been successfully implemented in production with at least one customerN
Deliverables

Customer deliverables include the following:

  • Design file (encrypted source code or post-synthesis netlist)
  • Simulation model for ModelSim Altera edition
  • Timing and/or layout constraints
  • Testbench or design example
  • Documentation with revision control
  • Readme file
Y
Any additional customer deliverables provided with IP
Optional Verification IP
Parameterization GUI allowing end user to configure IPN
IP core is enabled for OpenCore Plus SupportY
Source language
Verilog
Testbench languageVerilog
Software drivers providedY
Driver OS supportLinux
Implementation
User InterfaceOther: Custom data bus
IP-XACT Metadata includedN
Verification
Simulators supportedMentor Graphics (Modelsim, Questa)
Hardware validated Y. Altera Board Name HiTech Global: HTG-S5-PCIE-A7
Industry standard compliance testing performed
N
If No, is it planned?Y
Interoperability
IP has undergone interoperability testing
Y
Interoperability reports available  N

Design Solutions Network Members provide products and/or services that are sold or licensed by the Member and not Altera or its affiliates. Altera and its affiliates hereby disclaim any express or implied warranty of any kind including warranties of merchantability, noninfringement of intellectual property, or fitness for any particular purpose with respect to any such products and/or services.