The Ultra-Low Latency Ethernet MAC and PCS is the industry leading solution for latency critical Ethernet applications such as high-frequency trading and data center Ethernet switches. The core is designed using advanced techniques leading to unmatched, ultra-low gate count utilization and amazing latency performances. The IP core supports full wire line speed with a 64-byte packet length. It also supports back-to-back or mixed length traffic, up to jumbo frame size, with no dropped packets.
Complete Stratix-V reference design available including: - 40G MAC & PCS IP integrated with high-speed transceivers, clock and CPU interface - Software Command Line Interface (CLI) to configure and monitor statistics - Simple RTL test benches (optional Verification IP - UVM based) - Product documentation, register mapping.
IP Quality Metrics
|Year IP was first released||2016|
|Latest version of Quartus supported||15.1|
|Altera Customer Use|
|IP has been successfully implemented in production with at least one customer||N|
Customer deliverables include the following:
|Any additional customer deliverables provided with IP||Optional Verification IP|
|Parameterization GUI allowing end user to configure IP||N|
|IP core is enabled for OpenCore Plus Support||Y|
|Software drivers provided||Y|
|Driver OS support||Linux|
|User Interface||Other: Custom data bus|
|IP-XACT Metadata included||N|
|Simulators supported||Mentor Graphics (Modelsim, Questa)|
|Hardware validated||Y. Altera Board Name HiTech Global: HTG-S5-PCIE-A7|
|Industry standard compliance testing performed||N|
|If No, is it planned?||Y|
|IP has undergone interoperability testing||Y|
|Interoperability reports available||N|
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