Channelized Multi-Port 1/10G Ethernet MAC

Block Diagram

Solution Type: IP Core

End Market: Broadcast, Computer & Storage, Consumer, Industrial, Military, Test & Measurement, Wireless, Wireline

Evaluation Method: OpenCore Plus, Source Code

Technology: Interface Protocols: Ethernet

Arria Series: Arria 10, Arria 10 SoC

Stratix Series: Stratix V

Segments: 

Supported Device Family: 

Solution Type: 

Overview

This IP core is a high performance Multi-port 1 / 10-Gbps Ethernet media access controller (MAC). The core is designed using timeslice techniques resulting in extremely efficient area and resource utilization compared to standard solutions. The number of ports is flexible and can easily be customized as required. Standard number of port supported are 4, 8 and 16 ports at 1-Gbps and 2, 4 and 8 ports at 10-Gbps.

Features

  • Multi-port Ethernet MAC supporting 1GbE and 10GbE
  • Highly optimized implementation resulting in very low gate count and high timing margin, even on slowest FPGA speed grade
  • Standard GMII and XGMII interfaces between MAC and PCS
  • Programmable Tx and Rx path VLAN detection (Programmable TPID, stacked VLAN)
  • Configurable statistics vector and collector on transmit and receive MAC/PCS data

Device Utilization and Performance

Area (1) / Performances: LUTs FFs BRAM Latency [ns] 4 x 1-GbE\t2,664\t3,150\t2\t 280ns 8 x 1-GbE\t3,620\t3,816\t2\t 260ns 16 x 1-GbE\t6,024\t6,746\t2\t 424ns 2 x 10-GbE\t3,529\t3,707\t2\t 108ns 4 x 10-GbE\t5,576\t5,628\t2\t 172ns 8 x 10-GbE\t10,579\t9,269\t10\t 238ns Note: timing margin > 20% (Stratix-V slowest speed grade)

Getting Started

Verification IP - UVM based with associated test cases Product documentation, register mapping, SW drivers.

IP Quality Metrics

Basic
Year IP was first released2016
Latest version of Quartus supported15.1
Altera Customer Use
IP has been successfully implemented in production with at least one customerN
Deliverables

Customer deliverables include the following:

  • Design file (encrypted source code or post-synthesis netlist)
  • Simulation model for ModelSim Altera edition
  • Timing and/or layout constraints
  • Testbench or design example
  • Documentation with revision control
  • Readme file
Y
Any additional customer deliverables provided with IP
Optional Verification IP
Parameterization GUI allowing end user to configure IPN
IP core is enabled for OpenCore Plus SupportY
Source language
Verilog
Testbench languageVerilog
Software drivers providedY
Driver OS supportLinux
Implementation
User InterfaceOther: Channelizez data bus
IP-XACT Metadata includedN
Verification
Simulators supportedMentor Graphics (Modelsim, Questa)
Hardware validated N. Altera Board Name HiTech Global: HTG-S5-PCIE-A7
Industry standard compliance testing performed
N
If No, is it planned?Y
Interoperability
IP has undergone interoperability testing
N
Interoperability reports available  N

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