Ultra-Low Latency 10G Ethernet MAC & PCS

Block Diagram

Solution Type: IP Core

End Market: Broadcast, Computer & Storage, Consumer, Industrial, Military, Test & Measurement, Wireless, Wireline

Evaluation Method: OpenCore Plus, Source Code

Technology: Interface Protocols: Ethernet

Arria Series: Arria 10, Arria 10 SoC

Stratix Series: Stratix V


10G MAC + PCS (10GBASE-R) The Ultra-Low Latency Ethernet MAC and PCS is the industry leading solution for latency critical Ethernet applications such as high-frequency trading and data center Ethernet switches. The core is designed using advanced techniques leading to unmatched, ultra-low gate count utilization and amazing latency performances. The IP core supports full wire line speed with a 64-byte packet length. It also supports back-to-back or mixed length traffic, up to jumbo frame size, with no dropped packets.


    Device Utilization and Performance

    Area (1) 3,027 (LUTS) 3,642 (FF) 0 (BRAM) Clock = 312.5MHz Timing margin = 20% (2) Latency = 38.4ns (MAC+PCS, round trip) 1 Resources utilization includes internal statistics counters 2 Timing margin is based on Altera Stratix-V mid-speed grade device

    Getting Started

    Complete Stratix-V reference design available including: - 10G MAC & PCS IP integrated with high-speed transceivers, clock/PLLs and CPU interface - Software Command Line Interface (CLI) to configure MAC/PCS and monitor statistics - Simple RTL test benches (optional Verification IP - UVM based) - Product documentation, register mapping.

    IP Quality Metrics

    Year IP was first released2016
    Latest version of Quartus supported15.1
    Altera Customer Use
    IP has been successfully implemented in production with at least one customerN

    Customer deliverables include the following:

    • Design file (encrypted source code or post-synthesis netlist)
    • Simulation model for ModelSim Altera edition
    • Timing and/or layout constraints
    • Testbench or design example
    • Documentation with revision control
    • Readme file
    Any additional customer deliverables provided with IP
    Optional Verification IP
    Parameterization GUI allowing end user to configure IPN
    IP core is enabled for OpenCore Plus SupportY
    Source language
    Testbench languageVerilog
    Software drivers providedY
    Driver OS supportLinux
    User InterfaceAXI; Other: Custom
    IP-XACT Metadata includedN
    Simulators supportedMentor Graphics (Modelsim, Questa)
    Hardware validated Y. Altera Board Name HiTech Global: HTG-S5-PCIE-A7
    Industry standard compliance testing performed
    If No, is it planned?Y
    IP has undergone interoperability testing
    Interoperability reports available  N

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