XpressRICH3

Block Diagram

Solution Type: IP Core

End Market: Automotive, Broadcast, Computer & Storage, Consumer, Industrial, Medical, Military, Test & Measurement, Wireless, Wireline

Evaluation Method: Source Code

Technology: Interface Protocols: PCI Express

Arria Series: Arria 10, Arria V

Stratix Series: Stratix V

Overview

XpressRICH3 is a highly configurable PCIe interface Soft IP designed for ASIC and FPGA implementations. With advanced features such as SR-IOV and data-path protection, and numerous tape-outs on leading edge process technologies, XpressRICH3 is the industry’s PCIe IP of choice for enterprise-class applications requiring the highest performance, reliability, and flexibility.

Features

    Device Utilization and Performance

    Contact us to know the device utilization and Performance for your configuration

    Getting Started

    Available

    IP Quality Metrics

    Basic
    Year IP was first released2012
    Latest version of Quartus supported15.1
    Altera Customer Use
    IP has been successfully implemented in production with at least one customerY
    Deliverables

    Customer deliverables include the following:

    • Design file (encrypted source code or post-synthesis netlist)
    • Simulation model for ModelSim Altera edition
    • Timing and/or layout constraints
    • Testbench or design example
    • Documentation with revision control
    • Readme file
    Y
    Parameterization GUI allowing end user to configure IPY
    IP core is enabled for OpenCore Plus SupportN
    Source language
    Verilog
    Testbench languageVerilog
    Software drivers providedY
    Driver OS supportLinux, Windows
    Implementation
    User InterfaceOther: Tx/Rx
    IP-XACT Metadata includedN
    Verification
    Simulators supportedPLDA
    Hardware validated Y. Altera Board Name XpressGX5LP
    Industry standard compliance testing performed
    Y
    If yes, which test(s)?PCI-SIG
    If yes, on which Altera device(s)?STRATIX V
    If Yes, date performed
    10/03/2013
    Interoperability
    IP has undergone interoperability testing
    Y
    Interoperability reports available  Y

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