RapidIO 2.x LP-Serial Physical Layer Endpoint Core

Block Diagram

Solution Type: IP Core

End Market: Computer & Storage, Medical, Military, Wireless

Evaluation Method: OpenCore, OpenCore Plus

Technology: Interface Protocols: RapidIO

Arria Series: Arria 10, Arria 10 SoC

Cyclone Series: Cyclone V, Cyclone V SoC

Stratix Series: Stratix V

Overview

The LP-Serial Endpoint Core implements all of the functions are defined in the RapidIO Physical Layer LP-Serial Specification Rev. 2.2. Figure 1 illustrates the overall architecture of the core. The core integrates an IO Logical Layer Initiator that maps AXI4 transactions into RapidIO IO Logical request packets. The user interface consists of a 64-bit or 128-bit AXI4 slave interface. The core also integrates an IO Logical Layer Target that maps RapidIO IO Logical request packets into AXI4 transactions on the user interface. This user interface consists of a 64-bit or 128-bit AXI4 master interface. In addition to the RapidIO Physical layer functions, the core also includes Management Module that supports access to Physical, Transport, and Logical Layer CSRs either through maintenance transactions, or through the AXI4-lite Local Management Interface (LMI).

Features

    Device Utilization and Performance

    Varies widely with options chosen. Contact Praesum for utilization for your configuration.

    Getting Started

    Evaluation design pre-integrated with Linux demo application for Cyclone V SOC on Arrow SocKit board.

    IP Quality Metrics

    Basic
    Year IP was first released2004
    Latest version of Quartus supported15.1
    Altera Customer Use
    IP has been successfully implemented in production with at least one customerY
    Deliverables

    Customer deliverables include the following:

    • Design file (encrypted source code or post-synthesis netlist)
    • Simulation model for ModelSim Altera edition
    • Timing and/or layout constraints
    • Testbench or design example
    • Documentation with revision control
    • Readme file
    Y
    Parameterization GUI allowing end user to configure IPY
    IP core is enabled for OpenCore Plus SupportY
    Source language
    Verilog
    Testbench languageVerilog
    Software drivers providedY
    Driver OS supportLinux
    Implementation
    User InterfaceAXI
    IP-XACT Metadata includedY
    Verification
    Simulators supportedModelsim / Questa
    Hardware validated Y. Altera Board Name Arrow SocKit
    Industry standard compliance testing performed
    N
    If No, is it planned?N
    Interoperability
    IP has undergone interoperability testing
    Y
    Interoperability reports available  Y

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