JPEG IP Core

Block Diagram

Solution Type: IP Core

End Market: Automotive, Broadcast, Computer & Storage, Consumer, Industrial, Medical

Evaluation Method: Source Code

Technology: DSP: Video and Image Processing

Arria Series: Arria 10, Arria V, Arria 10 SoC, Arria V SoC

Cyclone Series: Cyclone IV, Cyclone V, Cyclone V SoC

MAX Series: MAX 10

Stratix Series: Stratix IV, Stratix V

Overview

We have a variety of IP cores: JPEG IP core with liabilities and achievements over 10 years since the birth of this trustworthy image file format worldwide, JPEG XR IP core in conformity of the format for the next generation. We also provide customers with services developing customized cores and customizing cores themselves. •JPEG Baseline IP Core   This IP core complies with the JPEG Baseline format and compresses/ decompresses still images. •JPEG EXTENDED IP Core   This IP core complies with the JPEG Extended DCT-based format and compresses/ decompresses the 8/ 12-bit images. •Lossless JPEG IP Core   This IP core complies with the Lossless JPEG format (ITU-T T.81 Annex H) and compresses/ decompresses still images without deterioration. •JPEG XR IP Core    The IP core complying with JPEG XR format (ISO/IEC 29199-2), a new still image compression/decompression format following JPEG and JPEG 2000.

Features

    Device Utilization and Performance

    Refer http://www.shikino.co.jp/eng/products/JPEG-IP%20Leaflet_Ver1.01E_HP.pdf

    Getting Started

    For additional information, contact Shikino High-Tech Co., Ltd. Email:ip_sales@shikino.co.jp http://www.shikino.co.jp/eng/products/ip-1.html

    IP Quality Metrics

    Basic
    Year IP was first released2000
    Latest version of Quartus supported15.1
    Altera Customer Use
    IP has been successfully implemented in production with at least one customerY
    Deliverables

    Customer deliverables include the following:

    • Design file (encrypted source code or post-synthesis netlist)
    • Simulation model for ModelSim Altera edition
    • Timing and/or layout constraints
    • Testbench or design example
    • Documentation with revision control
    • Readme file
    Y
    Parameterization GUI allowing end user to configure IPN
    IP core is enabled for OpenCore Plus SupportN
    Source language
    Verilog
    Testbench languageVerilog
    Software drivers providedN
    Driver OS support-
    Implementation
    User InterfaceOther: Original
    IP-XACT Metadata includedN
    Verification
    Simulators supportedNC-Verilog
    Hardware validated N. Altera Board Name NULL
    Industry standard compliance testing performed
    Y
    If yes, which test(s)?JPEG Part2(ISO/IEC10918-2
    If yes, on which Altera device(s)?Stratix IV
    If Yes, date performed
    10/01/2012
    Interoperability
    IP has undergone interoperability testing
    N
    Interoperability reports available  N

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