TCP OFFLOAD ENGINE - TOEFX101

Block Diagram

Solution Type: IP Core

End Market: Automotive, Broadcast, Computer & Storage, Industrial, Medical, Military, Test & Measurement, Wireless, Wireline

Evaluation Method: Source Code

Technology: Basic Functions: Miscellaneous

Stratix Series: Stratix V

Segments: 

Supported Device Family: 

Solution Type: 

Overview

TOE-FX101 (1G/10G LOW LATENCY TCP/IP OFFLOAD ENGINE IP-CORE) is an ultra-low latency TCP-IP core engine designed for high-performances network applications. The IP core can interface local area networks at 1G or 10G Ethernet by performing basic Ethernet and Internet Protocol (ARP, ICMP) and RFC based TCP protocol. The TCP payload is delivered to the User Interface with <100 ns latency. The UI is based on internal BRAM VHDL interface for a quick setup of the IP CORE and easy send/receive operation to develop your full custom hardware application.

Features

    Device Utilization and Performance

    Design implemented: TOEFX101 1G version, 8 TCP session, 32KB of WIN SIZE for each session. Device/Board implemented: Stratix V GX A7, TERASIC DE5-NET. Device utilization: Logic utilization (in ALMs) = 22744.2 (8.9%), Total block memory bits = 4190192 (8.0%), Total DSP Blocks = 5 (1.9%). Performance measured (TOE configured in ECHO, CPU core I7 Windows 7 64 bits, implementing RX/TX client): continuous sustained rate: 533 Mbit/sec.

    Getting Started

    Free evaluation sof file configured in TEST ECHO mode. Trial version already available for TERASIC DE5-NET board. Other board implementation available on request. User manual document. Please contact Sky Technology for further details.

    IP Quality Metrics

    Basic
    Year IP was first released2016
    Latest version of Quartus supported15.1
    Altera Customer Use
    IP has been successfully implemented in production with at least one customerY
    Deliverables

    Customer deliverables include the following:

    • Design file (encrypted source code or post-synthesis netlist)
    • Simulation model for ModelSim Altera edition
    • Timing and/or layout constraints
    • Testbench or design example
    • Documentation with revision control
    • Readme file
    N
    Parameterization GUI allowing end user to configure IPN
    IP core is enabled for OpenCore Plus SupportN
    Source language
    VHDL
    Testbench languageVHDL
    Software drivers providedN
    Driver OS supportNo CPU needed
    Implementation
    User InterfaceOther: Custom, BRAM based.
    IP-XACT Metadata includedN
    Verification
    Simulators supportedModelsim
    Hardware validated Y. Altera Board Name TERASIC DE5-NET
    Industry standard compliance testing performed
    N
    If No, is it planned?Y
    Interoperability
    IP has undergone interoperability testing
    Y
    Interoperability reports available  Y

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