H.264/AVC HD Decoder IP Core

Block Diagram

Solution Type: IP Core

End Market: Automotive, Broadcast, Computer & Storage, Industrial, Medical, Military, Wireless, Wireline

Evaluation Method: Source Code

Technology: DSP: Video and Image Processing

Arria Series: Arria 10, Arria V, Arria 10 SoC, Arria V SoC

Cyclone Series: Cyclone IV, Cyclone V, Cyclone V SoC

Stratix Series: Stratix IV, Stratix V

Segments: 

Supported Device Family: 

Solution Type: 

Overview

SOC provides a high-performance H.264/AVC decoder IP core that supports all Intel FPGA families that have sufficient logic resources. Video transmission (UDP/IP + Ethernet) cores are available. SOC also supplies all-in-one H.264 decoder modules, which are System-on-Module (SoM) cards based on the SOC codec IP cores and Intel FPGAs.

Features

  • High, Mail and Baseline Profiles
  • Zero latency (0.25ms)
  • Small silicon footprint (25-30kALMs)
  • Low power (less than 1w, for HD resolutions)
  • UDP/IP+Ethernet available

Device Utilization and Performance

Logic=30k ALMs; Block RAM=2.5Mbits; DSP=25DSPs. Performance: Standard=H.264/AVC (ISO/IEC14496-10); Profiles=High (Main, Baseline); Resolution=HD (1080p upto 120fps); Chroma=4:2:2/4:2:0; Precision=8/10 bits; Audio=AAC or MPEG-2 Layer-II; Latency=0.25ms.

Getting Started

SOC supplies plug-and-play evaluation kits for the H.264 decoder IP core. SOC web page: http://www.soctechnologies.com/eval-kits/h264_hd_decoder_kit

IP Quality Metrics

Basic
Year IP was first released2011
Latest version of Quartus supported17.0
Altera Customer Use
IP has been successfully implemented in production with at least one customerY
Deliverables

Customer deliverables include the following:

  • Design file (encrypted source code or post-synthesis netlist)
  • Simulation model for ModelSim Altera edition
  • Timing and/or layout constraints
  • Testbench or design example
  • Documentation with revision control
  • Readme file
Y
Any additional customer deliverables provided with IP
PCB reference Designs
Parameterization GUI allowing end user to configure IPY
IP core is enabled for OpenCore Plus SupportN
Source language
VHDL
Testbench languageVHDL
Software drivers providedY
Driver OS supportLinux
Implementation
User InterfaceAXI; Avalon-MM
IP-XACT Metadata includedY
Verification
Simulators supportedModelsim
Hardware validated Y. Altera Board Name Cyclone V, Cyclone 10, Arria V, Arria 10, Stratix IV, Stratix V
Industry standard compliance testing performed
Y
If yes, which test(s)?MPEG
If yes, on which Altera device(s)?Cyclone V
If Yes, date performed
05/01/2012
Interoperability
IP has undergone interoperability testing
Y
Interoperability reports available  Y
classtest

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