H.264 Decoder IP Core

Block Diagram

Solution Type: IP Core

End Market: Automotive, Broadcast, Computer & Storage, Industrial, Medical, Military, Wireless, Wireline

Evaluation Method: Source Code

Technology: DSP: Video and Image Processing

Arria Series: Arria 10, Arria V, Arria 10 SoC, Arria V SoC

Cyclone Series: Cyclone IV, Cyclone V, Cyclone V SoC

Stratix Series: Stratix IV, Stratix V

Segments: 

Supported Device Family: 

Solution Type: 

Overview

SOC provides a high-performance H.264 decoder IP core that supports all Intel (Altera) FPGA families that have sufficient logic resources. Key features of the SOC H.264 decoder IP core include: •\t High-profile, main-profile, and baseline-profile •\t Zero latency (0.25ms) •\t Small silicon footprint (less than 30kAMLs) •\t Low Power (less than 1w, for HD resolution) •\t High reliability (All hardware engine in Intel FPGA) •\t Supports HD and 4k resolutions •\t User controllable API •\t Video transmission (UDP/IP + Ethernet) cores available SOC also supplies all-in-one H.264 decoder modules, which are System-on-Module (SoM) cards based on the SOC codec IP cores and Intel FPGAs. The modules can be connected to user devices/PCBs using standard SODIMM connectors. Based on the SOC codec IP cores and Intel FPGAs, SOC also developed codec chipsets (SOC-McodecTM) that function as AISC chips. Standard H.264 decoder chipsets for different specifications are available. SOC also

Features

    Device Utilization and Performance

    Device Utilization: Logic Resources: 30kALMs Block RAMs: 2.5Mbits DSPs: 25DSPs Performance: Standard: \t\t \tH.264/AVC (ISO/IEC14496-10) Video Encoder Profiles: \tHigh, Main, Baseline Input Bit Rates:\t\t1-400Mbps & above Video Resolutions:\t \tHD 1080p upto 120fps, 4k upto 60fps Chroma Formats: \t\t4:2:2 or 4:2:0 Precision:\t\t \t8 bits or 10 bits Input Format:\t\t\tH.264 Elementary, or Transport Stream Video output Format:\t \tYUV or RGB Audio Support: \t\tAAC or MPEG-2 Layer-II Latency:\t \t \t0.25ms Power Consumption: \t700mw-2w (Core only) Target FPGAs:\t \t\tCyclone V, Cyclone 10, Arria V, Arria 10, Stratix IV, Stratix V

    Getting Started

    SOC supplies plug-and-play evaluation kits for the H.264 decoder IP core (as well as for the decoder module and chipset). The product code for HD resolution decoder evaluation kit is: FMC-MCM-1000-H264-HD-DC SOC web page: http://www.soctechnologies.com/eval-kits/h264_hd_decoder_kit The product code for 4k resolution decoder evaluation kit is: VTR-4000C-H264-4k-DC SOC web page: http://www.soctechnologies.com/eval-kits/h264_4K_decoder_kit E-mail: sales@soctechnologies.com

    IP Quality Metrics

    Basic
    Year IP was first released2011
    Latest version of Quartus supported17.0
    Altera Customer Use
    IP has been successfully implemented in production with at least one customerY
    Deliverables

    Customer deliverables include the following:

    • Design file (encrypted source code or post-synthesis netlist)
    • Simulation model for ModelSim Altera edition
    • Timing and/or layout constraints
    • Testbench or design example
    • Documentation with revision control
    • Readme file
    Y
    Any additional customer deliverables provided with IP
    PCB reference Designs
    Parameterization GUI allowing end user to configure IPY
    IP core is enabled for OpenCore Plus SupportN
    Source language
    VHDL
    Testbench languageVHDL
    Software drivers providedY
    Driver OS supportLinux
    Implementation
    User InterfaceAXI; Avalon-MM
    IP-XACT Metadata includedY
    Verification
    Simulators supportedModelsim
    Hardware validated Y. Altera Board Name Cyclone V, Cyclone 10, Arria V, Arria 10, Stratix IV, Stratix V
    Industry standard compliance testing performed
    Y
    If yes, which test(s)?MPEG
    If yes, on which Altera device(s)?Cyclone V
    If Yes, date performed
    05/01/2012
    Interoperability
    IP has undergone interoperability testing
    Y
    Interoperability reports available  Y

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