H.265 Encoder IP Core

Block Diagram

Solution Type: IP Core

End Market: Automotive, Broadcast, Computer & Storage, Industrial, Medical, Military, Wireless, Wireline

Evaluation Method: Source Code

Technology: DSP: Video and Image Processing

Arria Series: Arria 10, Arria V, Arria 10 SoC, Arria V SoC

Stratix Series: Stratix IV, Stratix V


Supported Device Family: 

Solution Type: 


SOC provides a high-performance H.265/HEVC encoder IP core that supports all Intel (Altera) FPGA families that have sufficient logic resources. Key features of the SOC H.265 encoder IP core include: •\t Zero latency (0.25ms) •\t Small silicon footprint (less than 90kAMLs) •\t Slim version available at less than 60kALMs •\t Low power (less than 1.5w, for HD resolution) •\t High reliability (All hardware engine) •\t High-video quality •\t Supports HD, 4k and 8k resolutions •\t User controllable API •\t Video transmission (UDP/IP + Ethernet) cores available SOC also supplies all-in-one H.265 encoder modules, which are System-on-Module (SoM) cards based on the SOC codec IP cores and Intel FPGAs. The modules can be connected to user devices/PCBs using a standard SODIMM connector. The SOC codec chipsets (SOC-McodecTM) are AISC chips based on the SOC IP cores and Intel FPGAs. Standard H.265 encoder chipsets for different specifications are available. SOC also offers Evaluati


    Device Utilization and Performance

    Device Utilization: Logic Resources: 60-90kALMs Block RAMs: 10Mbits DSPs: 450DSPs Performance: Standard: \t\t \tH.265/HEVC Video Encoder Profiles: \tMain 8. 10, and 12 profiles Output Bit Rates:\t\t1-100Mbps & above Video Resolutions:\t \tHD 1080p upto 120fps, 4k upto 60fps Chroma Formats: \t\t4:2:2 or 4:2:0 Output Format:\t\tH.265 Elementary, or Transport Stream Video Input Format:\t \tYUV or RGB Audio Support: \t\tAAC or MPEG-2 Layer-II Latency:\t \t \t0.25ms Power Consumption: \t1.5w-3w (Core only) Target FPGAs:\t \t\tCyclone-10, Arria-5, Arria-10, Stratix-4, Stratix-5.

    Getting Started

    SOC supplies plug-and-play evaluation kits for the H.265 encoder IP core (as well as for the encoder modules and chipsets). The product code for HD resolution encoder evaluation kit is: FMC-MCM-1000-H265-HD-EC SOC web page: http://www.soctechnologies.com/ip-cores/ip-core-h265-encoder The product code for 4k resolution encoder evaluation kit is: VTR-4000C-H265-4k-EC SOC web page: E-mail: sales@soctechnologies.com

    IP Quality Metrics

    Year IP was first released2015
    Latest version of Quartus supported17.0
    Altera Customer Use
    IP has been successfully implemented in production with at least one customerY

    Customer deliverables include the following:

    • Design file (encrypted source code or post-synthesis netlist)
    • Simulation model for ModelSim Altera edition
    • Timing and/or layout constraints
    • Testbench or design example
    • Documentation with revision control
    • Readme file
    Any additional customer deliverables provided with IP
    PCB Reference Designs
    Parameterization GUI allowing end user to configure IPY
    IP core is enabled for OpenCore Plus SupportY
    Source language
    Testbench languageVHDL
    Software drivers providedY
    Driver OS supportLinux
    User InterfaceAXI; Avalon-MM
    IP-XACT Metadata includedY
    Simulators supportedModelsim
    Hardware validated Y. Altera Board Name Arria V, Arria 10, Stratix V
    Industry standard compliance testing performed
    If yes, which test(s)?MPEG Compliance
    If yes, on which Altera device(s)?Arria V
    If Yes, date performed
    IP has undergone interoperability testing
    Interoperability reports available  Y

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