The USB 2.0 Host Controller IP Core is a 32-bit Avalon interface compliant core and supports ULPI interface. It supports High Speed (HS), Full Speed (FS) and Low Speed (LS) modes. IP core has been implemented in Verilog HDL and its functionality has been verified using different test cases in simulation environment as well as on hardware. It is provided as Altera Qsys Ready component and hence can be easily integrated in Qsys system.
1. Request an Evaluation version with License from http://www.slscorp.com/licensing/ip-licensing.html. 2. An email send to download the IP Core and the license file to compile the Quartus II design. 3. The IP Core installs documents including tutorial, software guide, reference design, Nios II driver and examples, Windows driver and examples and testing applications. 4. Integrate and test in your design. 5. Reference documents are also available at http://www.slscorp.com/downloads/category/115.html For any question or support, contact at firstname.lastname@example.org.
IP Quality Metrics
|Year IP was first released||2008|
|Latest version of Quartus supported||17.0|
|Altera Customer Use|
|IP has been successfully implemented in production with at least one customer||Y|
Customer deliverables include the following:
|Any additional customer deliverables provided with IP||Nios II object driver file, Linux driver and sample application files|
|Parameterization GUI allowing end user to configure IP||Y|
|IP core is enabled for OpenCore Plus Support||Y|
|Software drivers provided||Y|
|Driver OS support||Linux|
|IP-XACT Metadata included||N|
|Simulators supported||Altera ModelSim|
|Hardware validated||Y. Altera Board Name http://www.slscorp.com/products/development-boards/corecommander.html|
|Industry standard compliance testing performed||N|
|If No, is it planned?||Y|
|IP has undergone interoperability testing||N|
|Interoperability reports available||N|
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