Embedded USB 3.0/3.1 Gen 1 Host Controller

Block Diagram

Solution Type: IP Core

End Market: Computer & Storage, Consumer, Industrial, Medical, Military, Test & Measurement, Wireline

Evaluation Method: OpenCore Plus

Technology: Interface Protocols: Communications

Arria Series: Arria V, Arria V SoC

Cyclone Series: Cyclone IV, Cyclone V, Cyclone V SoC

Stratix Series: Stratix IV, Stratix V

Segments: 

Supported Device Family: 

Solution Type: 

Overview

USB 3.1 Gen 1 (USB 3.0) Embedded Host Controller IP Core is a 32-bit Avalon interface compliant core and supports PIPE interface. It has been adapted from xHCI v1.1 specification to be compact to meet embedded application needs. It is provided as Altera Qsys ready component and can be easily integrated in Qsys based system.

Features

  • Supports Super Speed (5 Gbps) mode, Adapted from xHCI v1.1 Specification
  • Supports Control and Bulk transfers, Integrated DMA Configurator, Supports PIPE interface
  • Supports Asynchronous Avalon clock interface, Supports External PHY for USB 3.1 Gen 1 (USB 3.0) PIPE Interface
  • Contains separate interface for Control Port and Data Port to improve Clock Domain Crossing (CDC) performance
  • Supports Avalon 32-bit Interface for Integrating in Qsys, Meets Altera Design Assistant guidelines

Device Utilization and Performance

Refer http://www.slscorp.com/ip-cores/communication/usb-3-0-3-1-gen-1-host-controller.html

Getting Started

1. Request an Evaluation version with License from http://www.slscorp.com/licensing/ip-licensing.html. 2. An email send to download the IP Core and the license file to compile the Quartus II design. 3. The IP Core installs documents including tutorial, software guide, reference design, Nios II driver and examples, Windows driver and examples and testing applications. 4. Integrate and test in your design. 5. Reference documents are also available at http://www.slscorp.com/downloads/category/151-usb-3-1-gen-1-usb-3-0-host-controller.html For any question or support, contact at support@slscorp.com.

IP Quality Metrics

Basic
Year IP was first released2016
Latest version of Quartus supported15.1
Altera Customer Use
IP has been successfully implemented in production with at least one customerN
Deliverables

Customer deliverables include the following:

  • Design file (encrypted source code or post-synthesis netlist)
  • Simulation model for ModelSim Altera edition
  • Timing and/or layout constraints
  • Testbench or design example
  • Documentation with revision control
  • Readme file
Y
Any additional customer deliverables provided with IP
USB xHCI drivers and sample files
Parameterization GUI allowing end user to configure IPY
IP core is enabled for OpenCore Plus SupportY
Source language
Verilog
Testbench languageVerilog
Software drivers providedY
Driver OS supportLinux
Implementation
User InterfaceAvalon-MM
IP-XACT Metadata includedN
Verification
Simulators supportedAltera ModelSim
Hardware validated Y. Altera Board Name http://www.slscorp.com/products/development-boards/usb-3-0-development-board.html
Industry standard compliance testing performed
N
If No, is it planned?Y
Interoperability
IP has undergone interoperability testing
N
Interoperability reports available  N

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