USB 3.0/3.1 Gen 1 standard is ubiquitous across the world and has raised the demand to implement it in various products. The integration of USB 3.0/3.1 Gen 1 Device with FPGA development board needs 60+ I/O for USB 3.0/3.1 Gen 1 PHY chip to connect it with FPGA. This adds an extra cost to the board. Altera has introduce the FPGA which has in built transceiver which run at 5Gbps speed (same as USB 3.1 Gen 1 (USB 3.0) Specification) with features like 8b/10b, SKIP control etc. required during implementing USB 3.0/3.1 Gen 1 Controller. SLS has integrate the USB 3.1 Gen 1 Device IP Core with the Altera Transceiver and USB 2.0 PHY chip, and developed the eUSB 3.1 Gen 1 Device Controller IP Core, offering low cost solution.
1. Request an Evaluation version with License from http://www.slscorp.com/licensing/ip-licensing.html. 2. An email send to download the IP Core and the license file to compile the Quartus II design. 3. The IP Core installs documents including tutorial, software guide, reference design, Nios II driver and examples, Windows driver and examples and testing applications. 4. Integrate and test in your design. 5. Reference documents are also available at http://www.slscorp.com/downloads/category/140-eusb-3-1-gen-1-eusb-3-0-device.html For any question or support, contact at email@example.com.
IP Quality Metrics
|Year IP was first released||2012|
|Latest version of Quartus supported||15.1|
|Altera Customer Use|
|IP has been successfully implemented in production with at least one customer||N|
Customer deliverables include the following:
|Any additional customer deliverables provided with IP||Nios II HAL Object Library & Application example, Windows Driver and Application example|
|Parameterization GUI allowing end user to configure IP||Y|
|IP core is enabled for OpenCore Plus Support||Y|
|Software drivers provided||Y|
|Driver OS support||Windows, Linux|
|IP-XACT Metadata included||N|
|Simulators supported||Altera ModelSim|
|Hardware validated||Y. Altera Board Name http://www.slscorp.com/products/development-boards/eusb30-development-board.html|
|Industry standard compliance testing performed||N|
|If No, is it planned?||Y|
|IP has undergone interoperability testing||N|
|Interoperability reports available||N|
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