Embedded USB 3.1 Gen 2 Device Controller (eUSB31SF)

Block Diagram

Solution Type: IP Core

End Market: Automotive, Computer & Storage, Consumer, Industrial, Medical, Military, Test & Measurement

Evaluation Method: OpenCore Plus

Technology: Interface Protocols: Communications

Arria Series: Arria 10, Arria V, Arria 10 SoC

Cyclone Series: Cyclone V

Segments: 

Supported Device Family: 

Solution Type: 

Overview

Leveraging the benefits of eUSB 3.0/3.1 Gen 1 device controller, eUSB 3.1 Gen 2 is designed using the Intel FPGA built-in 10 Gbps transceiver. It is a one-stop solution for all USB requirements ranging from USB 3.1 to USB 2.0. It supports SuperSpeed+ (SSP), SuperSpeed (SS), High Speed (HS) and Full Speed (FS) communication modes. The Core architecture allows to use minimal pins from FPGA for USB 3.1 interface with better stability. It provides USB 2.0 backward compatibility using an external USB 2.0 ULPI PHY. It has been designed to provide simplicity and flexibility along with highest throughput i.e. >7Gbps. Avalon interface allows to manage the control transfer using software, provides flexibility, while FIFO interface allows to transfer the data over non-control endpoint ensuring highest throughput.

Features

  • Supports SuperSpeed+ (SSP) and SuperSpeed (SS) modes
  • Uses Intel FPGA Device Transceiver as a PHY layer and thus eliminates need for external PHY for USB 3.1
  • Supports High, Full and Low Speed modes using External USB 2.0 PHY
  • Simple FIFO interface to transfer data over non-control endpoint. Capable to support up to 31 endpoints
  • Supported Device Family : Arria10 (Gen2 @10Gbps); Cyclone10(Gen2 @10Gbps); CycloneV(Gen1 @5Gbps); ArriaV(Gen1 @5Gbps)

Device Utilization and Performance

For Arria10 (up to Gen 2 10Gbps Interface) uses ~16244 ALM and ~76 M20K Memory. For Cyclone10 (up to Gen 2 10Gbps Interface) uses ~16395 ALM and ~73 M20K Memory. For Cyclone V (up to Gen 1 5Gbps Interface) uses ~5600 ALM and ~63 M10K Memory. For Arria V (up to Gen 1 5Gbps Interface) uses ~5510 ALM and ~66 M10K Memory.

Getting Started

1. Request an Evaluation version with License from http://www.slscorp.com/licensing/ip-licensing.html. 2. An email send to download the IP Core and the license file to compile the Quartus II design. 3. The IP Core installs documents including tutorial, software guide, reference design, Nios II driver and examples, Windows driver and examples and testing applications. 4. Integrate and test in your design. 5. Reference documents are also available at http://www.slscorp.com/ip-cores/communication/eusb-3-1-gen-2-device-controller-eusb31sf.html For any question or support, contact at support@slscorp.com.

IP Quality Metrics

Basic
Year IP was first released2016
Latest version of Quartus supported17.0
Altera Customer Use
IP has been successfully implemented in production with at least one customerY
Deliverables

Customer deliverables include the following:

  • Design file (encrypted source code or post-synthesis netlist)
  • Simulation model for ModelSim Altera edition
  • Timing and/or layout constraints
  • Testbench or design example
  • Documentation with revision control
  • Readme file
Y
Any additional customer deliverables provided with IP
Nios II HAL Object Library & Application example, Windows Driver and Application example
Parameterization GUI allowing end user to configure IPY
IP core is enabled for OpenCore Plus SupportY
Source language
Verilog
Testbench languageVerilog
Software drivers providedY
Driver OS supportWindows, Linux
Implementation
User InterfaceAvalon-MM
IP-XACT Metadata includedN
Verification
Simulators supportedModelSim for Intel FPGA
Hardware validated Y. Altera Board Name Intel Arria10GXKit;Intel Arria10 SoCKit; Intel Cyclone10GX Kit; CycloneV Dev Kit; iWave Arria 10 SOM
Industry standard compliance testing performed
N
If No, is it planned?Y
Interoperability
IP has undergone interoperability testing
N
Interoperability reports available  N

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