Leveraging the benefits of eUSB 3.0/3.1 Gen 1 device controller, eUSB 3.1 Gen 2 is designed using the Intel FPGA built-in 10 Gbps transceiver. It is a one-stop solution for all USB requirements ranging from USB 3.1 to USB 2.0. It supports SuperSpeed+ (SSP), SuperSpeed (SS), High Speed (HS) and Full Speed (FS) communication modes. The Core architecture allows to use minimal pins from FPGA for USB 3.1 interface with better stability. It provides USB 2.0 backward compatibility using an external USB 2.0 ULPI PHY. It has been designed to provide simplicity and flexibility along with highest throughput i.e. >7Gbps. Avalon interface allows to manage the control transfer using software, provides flexibility, while FIFO interface allows to transfer the data over non-control endpoint ensuring highest throughput.
1. Request an Evaluation version with License from http://www.slscorp.com/licensing/ip-licensing.html. 2. An email send to download the IP Core and the license file to compile the Quartus II design. 3. The IP Core installs documents including tutorial, software guide, reference design, Nios II driver and examples, Windows driver and examples and testing applications. 4. Integrate and test in your design. 5. Reference documents are also available at http://www.slscorp.com/ip-cores/communication/eusb-3-1-gen-2-device-controller-eusb31sf.html For any question or support, contact at email@example.com.
IP Quality Metrics
|Year IP was first released||2016|
|Latest version of Quartus supported||17.0|
|Altera Customer Use|
|IP has been successfully implemented in production with at least one customer||Y|
Customer deliverables include the following:
|Any additional customer deliverables provided with IP||Nios II HAL Object Library & Application example, Windows Driver and Application example|
|Parameterization GUI allowing end user to configure IP||Y|
|IP core is enabled for OpenCore Plus Support||Y|
|Software drivers provided||Y|
|Driver OS support||Windows, Linux|
|IP-XACT Metadata included||N|
|Simulators supported||ModelSim for Intel FPGA|
|Hardware validated||Y. Altera Board Name Arria 10 GX Development Kit, Cyclone V G/GX Development Kit, iWave Systems Arria 10 System On Module|
|Industry standard compliance testing performed||N|
|If No, is it planned?||Y|
|IP has undergone interoperability testing||N|
|Interoperability reports available||N|
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