Embedded USB 3.1 Gen 2 Device Controller (eUSB31SF)

Block Diagram

Solution Type: IP Core

End Market: Automotive, Computer & Storage, Consumer, Industrial, Medical, Military, Test & Measurement

Evaluation Method: OpenCore Plus

Technology: Interface Protocols: Communications

Arria Series: Arria 10, Arria V, Arria 10 SoC

Cyclone Series: Cyclone V


Leveraging the benefits of eUSB 3.0/3.1 Gen 1 device controller, eUSB 3.1 Gen 2 is designed using the Intel FPGA built-in 10 Gbps transceiver. It is a one-stop solution for all USB requirements ranging from USB 3.1 to USB 2.0. It supports SuperSpeed+ (SSP), SuperSpeed (SS), High Speed (HS) and Full Speed (FS) communication modes. The Core architecture allows to use minimal pins from FPGA for USB 3.1 interface with better stability. It provides USB 2.0 backward compatibility using an external USB 2.0 ULPI PHY. It has been designed to provide simplicity and flexibility along with highest throughput i.e. >7Gbps. Avalon interface allows to manage the control transfer using software, provides flexibility, while FIFO interface allows to transfer the data over non-control endpoint ensuring highest throughput.


    Device Utilization and Performance

    For Arria 10 (up to Gen 2 10Gbps Interface) uses ~16244 ALM and ~76 M20K Memory. For Cyclone V (up to Gen 1 5Gbps Interface) uses ~5600 ALM and ~63 M10K Memory.

    Getting Started

    1. Request an Evaluation version with License from http://www.slscorp.com/licensing/ip-licensing.html. 2. An email send to download the IP Core and the license file to compile the Quartus II design. 3. The IP Core installs documents including tutorial, software guide, reference design, Nios II driver and examples, Windows driver and examples and testing applications. 4. Integrate and test in your design. 5. Reference documents are also available at http://www.slscorp.com/ip-cores/communication/eusb-3-1-gen-2-device-controller-eusb31sf.html For any question or support, contact at support@slscorp.com.

    IP Quality Metrics

    Year IP was first released2016
    Latest version of Quartus supported17.0
    Altera Customer Use
    IP has been successfully implemented in production with at least one customerY

    Customer deliverables include the following:

    • Design file (encrypted source code or post-synthesis netlist)
    • Simulation model for ModelSim Altera edition
    • Timing and/or layout constraints
    • Testbench or design example
    • Documentation with revision control
    • Readme file
    Any additional customer deliverables provided with IP
    Nios II HAL Object Library & Application example, Windows Driver and Application example
    Parameterization GUI allowing end user to configure IPY
    IP core is enabled for OpenCore Plus SupportY
    Source language
    Testbench languageVerilog
    Software drivers providedY
    Driver OS supportWindows, Linux
    User InterfaceAvalon-MM
    IP-XACT Metadata includedN
    Simulators supportedModelSim for Intel FPGA
    Hardware validated Y. Altera Board Name Arria 10 GX Development Kit, Cyclone V G/GX Development Kit, iWave Systems Arria 10 System On Module
    Industry standard compliance testing performed
    If No, is it planned?Y
    IP has undergone interoperability testing
    Interoperability reports available  N

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