I2C Controller

Block Diagram

Solution Type: IP Core

End Market: Computer & Storage, Consumer, Industrial, Medical, Military, Test & Measurement, Wireless, Wireline

Evaluation Method: OpenCore Plus

Technology: Interface Protocols: Serial

Arria Series: Arria 10, Arria V

Cyclone Series: Cyclone IV, Cyclone V

MAX Series: MAX 10, MAX V

Stratix Series: Stratix IV, Stratix V

Segments: 

Supported Device Family: 

Solution Type: 

Overview

I2C (Inter-Integrated Circuit) Controller is a two-wire, bi-directional serial bus that provides simple and efficient method of data transmission over a short distance between many devices. Avalon compliant I2C Controller provides an interface between Nios II processor and I2C device. It can work as Master/Slave transmitter or Master/Slave receiver depending on working mode determined by Nios II processor. The I2C Controller IP core incorporates all features required by the latest I2C specification including clock synchronization, arbitration, multi-master systems and Fast-speed transmission mode. It is provided as Altera Qsys ready component and integrates easily into any Qsys generated system.

Features

  • Automatic detection and adoption to bus interface type, Multi-master operation
  • Compatible with Philips I2C(PCF 8584) standard, Supports both Master and Slave mode
  • Arbitration-lost interrupt with automatic transfer cancellation, Supports 7 bit addressing mode
  • Start/Stop/Repeated Start/Acknowledge generation and detection, Operates from wide range of input clock frequencies
  • Byte-by-byte data-transfer is driven by Interrupt or Bit-polling, Bus-Busy detection

Device Utilization and Performance

Refer http://www.slscorp.com/ip-cores/interface/i2c-controller.html

Getting Started

1. Request an Evaluation version with License from http://www.slscorp.com/licensing/ip-licensing.html. 2. An email send to download the IP Core and the license file to compile the Quartus II design. 3. The IP Core installs documents including tutorial, software guide, reference design, Nios II driver and examples, Windows driver and examples and testing applications. 4. Integrate and test in your design. 5. Reference documents are also available at http://www.slscorp.com/downloads/category/117.html For any question or support, contact at support@slscorp.com.

IP Quality Metrics

Basic
Year IP was first released2006
Latest version of Quartus supported15.1
Altera Customer Use
IP has been successfully implemented in production with at least one customerY
Deliverables

Customer deliverables include the following:

  • Design file (encrypted source code or post-synthesis netlist)
  • Simulation model for ModelSim Altera edition
  • Timing and/or layout constraints
  • Testbench or design example
  • Documentation with revision control
  • Readme file
Y
Any additional customer deliverables provided with IP
Nios II Example Files
Parameterization GUI allowing end user to configure IPY
IP core is enabled for OpenCore Plus SupportY
Source language
Verilog
Testbench languageVerilog
Software drivers providedY
Driver OS supportNone
Implementation
User InterfaceAvalon-MM
IP-XACT Metadata includedN
Verification
Simulators supportedAltera ModelSim
Hardware validated Y. Altera Board Name http://www.slscorp.com/products/development-boards/esdk.html
Industry standard compliance testing performed
N
If No, is it planned?Y
Interoperability
IP has undergone interoperability testing
N
Interoperability reports available  N

Design Solutions Network Members provide products and/or services that are sold or licensed by the Member and not Altera or its affiliates. Altera and its affiliates hereby disclaim any express or implied warranty of any kind including warranties of merchantability, noninfringement of intellectual property, or fitness for any particular purpose with respect to any such products and/or services.