Avalon compliant I2C Master IP core provides an interface between Nios II processor and an I2C Slave device. It can work as a master transmitter or master receiver depending on working mode determined by Nios II processor. The I2C Master IP core incorporates all features required by the latest I2C specification including clock synchronization, arbitration, multi-master systems and fast-speed transmission mode. The I2C Master IP core is provided as Altera Qsys ready component and integrates easily into any Qsys generated system.
1. Request an Evaluation version with License from http://www.slscorp.com/licensing/ip-licensing.html. 2. An email send to download the IP Core and the license file to compile the Quartus II design. 3. The IP Core installs documents including tutorial, software guide, reference design, Nios II driver and examples, Windows driver and examples and testing applications. 4. Integrate and test in your design. 5. Reference documents are also available at http://www.slscorp.com/downloads/category/119.html For any question or support, contact at email@example.com.
IP Quality Metrics
|Year IP was first released||2007|
|Latest version of Quartus supported||15.1|
|Altera Customer Use|
|IP has been successfully implemented in production with at least one customer||Y|
Customer deliverables include the following:
|Any additional customer deliverables provided with IP||Nios II Example Files|
|Parameterization GUI allowing end user to configure IP||Y|
|IP core is enabled for OpenCore Plus Support||Y|
|Software drivers provided||Y|
|Driver OS support||None|
|IP-XACT Metadata included||N|
|Simulators supported||Altera ModelSim|
|Hardware validated||Y. Altera Board Name http://www.slscorp.com/products/development-boards/esdk.html|
|Industry standard compliance testing performed||N|
|If No, is it planned?||Y|
|IP has undergone interoperability testing||N|
|Interoperability reports available||N|
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