I2S Controller

Block Diagram

Solution Type: IP Core

End Market: Automotive, Broadcast, Computer & Storage, Consumer, Industrial, Medical, Military, Test & Measurement, Wireline

Evaluation Method: OpenCore Plus

Technology: Interface Protocols: Serial

Arria Series: Arria 10, Arria V

Cyclone Series: Cyclone IV, Cyclone V

MAX Series: MAX 10, MAX V

Stratix Series: Stratix IV, Stratix V

Segments: 

Supported Device Family: 

Solution Type: 

Overview

I2S Controller is designed to transfer audio data to and from Audio codec. It can be configured as both Master and Slave mode using software. The I2S IP is Phillips Inter IC Sound (I2S) specification compliant core for Altera devices. It is provided as Altera Qsys ready component and integrates easily into any Qsys generated system.

Features

  • 8-bit and 16-bit sampling data width support
  • Variable sampling rate support, Used in both master/slave mode
  • Internal two 64 x 32 bit FIFO for data buffering
  • 32-bit DMA engine for both data transmit and receive for reducing CPU overhead
  • Transmit and Receive Operation, Compliant with the Avalon bus, Left and Right channel support

Device Utilization and Performance

Refer http://www.slscorp.com/ip-cores/interface/i2s-controller.html

Getting Started

1. Request an Evaluation version with License from http://www.slscorp.com/licensing/ip-licensing.html. 2. An email send to download the IP Core and the license file to compile the Quartus II design. 3. The IP Core installs documents including tutorial, software guide, reference design, Nios II driver and examples, Windows driver and examples and testing applications. 4. Integrate and test in your design. 5. Reference documents are also available at http://www.slscorp.com/downloads/category/121.html For any question or support, contact at support@slscorp.com.

IP Quality Metrics

Basic
Year IP was first released2006
Latest version of Quartus supported15.1
Altera Customer Use
IP has been successfully implemented in production with at least one customerN
Deliverables

Customer deliverables include the following:

  • Design file (encrypted source code or post-synthesis netlist)
  • Simulation model for ModelSim Altera edition
  • Timing and/or layout constraints
  • Testbench or design example
  • Documentation with revision control
  • Readme file
Y
Parameterization GUI allowing end user to configure IPY
IP core is enabled for OpenCore Plus SupportY
Source language
Verilog
Testbench languageVerilog
Software drivers providedY
Driver OS supportNone
Implementation
User InterfaceAvalon-MM
IP-XACT Metadata includedN
Verification
Simulators supportedAltera ModelSim
Hardware validated Y. Altera Board Name http://www.slscorp.com/products/development-boards/esdk.html, http://www.slscorp.com/products/santac
Industry standard compliance testing performed
N
If No, is it planned?Y
Interoperability
IP has undergone interoperability testing
N
Interoperability reports available  N
classtest

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