ONFI Controller

Block Diagram

Solution Type: IP Core

End Market: Computer & Storage, Consumer

Evaluation Method: OpenCore Plus

Technology: Memory Interfaces and Controllers: Flash

Cyclone Series: Cyclone IV

Segments: 

Supported Device Family: 

Solution Type: 

Overview

ONFI Controller IP Core is the intermediate stage between NAND Flash memory and master controller. It is designed to have high speed solution to manage Raw NAND Flash application. It supports Open NAND Flash Interface Working Group (ONFI) 2.2 standard. Two advanced architectures - register based and descriptor based provides high speed performance, flexibility, data integrity and device compatibility. Descriptor based architecture reduces amount of CPU intervention. The ONFI Controller IP Core gives full support for Altera's Qsys based systems and provides communication between processor and NAND Flash device using Avalon interface.

Features

  • Supports up to 4 NAND Flash device selection, Supports 4KB and 8KB page size
  • Supports command repeat and auto address increment functionality, Supports Multiplane (interleave) and Multi LUN operation
  • Supports 8 bit data bus, Supports 4, 8 and 12 bit Error Correction per 512 bytes
  • Buffer with configurable buffer depth for read and write operation, Supports interrupt driven functionality
  • Supports ONFI 2.3 standard command set, Supports integrated 32 bit DMA interface selection

Device Utilization and Performance

Refer http://www.slscorp.com/ip-cores/memory/nand-flash/onfi-controller.html

Getting Started

1. Request an Evaluation version with License from http://www.slscorp.com/licensing/ip-licensing.html. 2. An email send to download the IP Core and the license file to compile the Quartus II design. 3. The IP Core installs documents including tutorial, software guide, reference design, Nios II driver and examples, Windows driver and examples and testing applications. 4. Integrate and test in your design. 5. Reference documents are also available at http://www.slscorp.com/downloads/category/128.html For any question or support, contact at support@slscorp.com.

IP Quality Metrics

Basic
Year IP was first released2009
Latest version of Quartus supported15.1
Altera Customer Use
IP has been successfully implemented in production with at least one customerN
Deliverables

Customer deliverables include the following:

  • Design file (encrypted source code or post-synthesis netlist)
  • Simulation model for ModelSim Altera edition
  • Timing and/or layout constraints
  • Testbench or design example
  • Documentation with revision control
  • Readme file
Y
Parameterization GUI allowing end user to configure IPY
IP core is enabled for OpenCore Plus SupportY
Source language
Verilog
Testbench languageVerilog
Software drivers providedY
Driver OS supportNone
Implementation
User InterfaceAvalon-MM
IP-XACT Metadata includedN
Verification
Simulators supportedAltera ModelSim
Hardware validated Y. Altera Board Name SLS USB 3.0 development board, Stratix IV GX Development Kit, Cyclone III Starter Kit
Industry standard compliance testing performed
N
If No, is it planned?Y
Interoperability
IP has undergone interoperability testing
N
Interoperability reports available  N

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