USB 1.1 Device, Software based enumeration, RAM Interface (USB11SR)

Block Diagram

Solution Type: IP Core

End Market: Computer & Storage, Consumer, Industrial, Military, Test & Measurement, Wireline

Evaluation Method: OpenCore Plus

Technology: Interface Protocols: Communications

Arria Series: Arria V

Cyclone Series: Cyclone IV, Cyclone V

MAX Series: MAX 10, MAX V

Stratix Series: Stratix IV, Stratix V


Supported Device Family: 

Solution Type: 


The USB 1.1 Device, Software Based Enumeration IP Core is RAM based USB 1.1 device core with 32-bit Avalon interface. The core supports Full Speed (12 Mbps) functionality and Low Speed (1.5 Mbps) functionality can be added as per customer request with additional charges. The core supports three preconfigured Control, Bulk IN and Bulk OUT endpoints. It can be configurable for up to 15 IN/OUT endpoints on customer request on chargeable basis. Each configurable endpoints has an endpoint controller that supports Interrupt, Bulk and Isochronous transfers. The core has been optimized for Altera FPGAs and its functionality has been verified on the hardware with Altera Quartus II. The package includes ModelSim precompiled library for core simulation and verification.


  • Qsys based Encrypted IP Core
  • Windows Driver and Application Example (VC++)
  • Nios II HAL Driver (Object Code) and Application Example (C Code)
  • Reference Design and Technical Documents

Device Utilization and Performance

Cyclone III - 1900 LE, 8 M9K,103MHz, Cyclone IV - 1900 LE, 8 M9K, 109MHz, Cyclone V - 840 ALM, 8 M10K, 60MHz, Stratix III - 1300 ALUT, 8 M9K, 141MHz, Stratix IV - 1300 ALUT, 8 M9K, 130MHz, Stratix V - 800 ALM, 8 M20K, 100MHz, Arria II - 1300 ALUT, 8 M9K, 115MHz, Arria V - 830 ALM, 8 M10K, 83MHz, MAX 10 - 1900 LE, 8 M9K, 104MHz

Getting Started

1. Request an Evaluation version with License from 2. An email send to download the IP Core and the license file to compile the Quartus II design. 3. The IP Core installs documents including tutorial, software guide, reference design, Nios II driver and examples, Windows driver and examples and testing applications. 4. Integrate and test in your design. 5. Reference documents are also available at For any question or support, contact at

IP Quality Metrics

Year IP was first released2003
Latest version of Quartus supported15.1
Altera Customer Use
IP has been successfully implemented in production with at least one customerY

Customer deliverables include the following:

  • Design file (encrypted source code or post-synthesis netlist)
  • Simulation model for ModelSim Altera edition
  • Timing and/or layout constraints
  • Testbench or design example
  • Documentation with revision control
  • Readme file
Any additional customer deliverables provided with IP
Nios II HAL Object Library & Application example, Windows Driver and Application example
Parameterization GUI allowing end user to configure IPY
IP core is enabled for OpenCore Plus SupportY
Source language
Testbench languageVerilog
Software drivers providedY
Driver OS supportWindows, Linux
User InterfaceAvalon-MM
IP-XACT Metadata includedN
Simulators supportedAltera ModelSim
Hardware validated Y. Altera Board Name
Industry standard compliance testing performed
If No, is it planned?Y
IP has undergone interoperability testing
Interoperability reports available  N

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