USB 2.0 Device, Software based enumeration RAM Interface (USB20SR)

Block Diagram

Solution Type: IP Core

End Market: Computer & Storage, Consumer, Industrial, Medical, Military, Test & Measurement, Wireline

Evaluation Method: OpenCore Plus

Technology: Interface Protocols: Communications

Arria Series: Arria 10, Arria V, Arria 10 SoC, Arria V SoC

Cyclone Series: Cyclone IV, Cyclone V, Cyclone V SoC

MAX Series: MAX 10, MAX V

Stratix Series: Stratix IV, Stratix V


Supported Device Family: 

Solution Type: 


The USB 2.0 Device, Software Enumeration (USB20SR) IP Core is a RAM based USB 2.0 device core with 32-bit Avalon interface and ULPI interface support. The core supports both High Speed(480 Mbps) and Full Speed(12 Mbps) functionality. The core supports three preconfigured endpoints Control, IN, and OUT. It can be configured for up to 15 IN as well as OUT endpoints on customer's request at additional cost. IP core has been implemented in Verilog HDL and its functionality has been verified using different test cases in simulation environment as well as on hardware. It is provided as Altera Qsys Ready component and hence can be easily integrated in Qsys system. The package includes ModelSim pre-compiled library of Host-BFM with predefined test cases for IP core simulation and verification.


  • Qsys based Encrypted IP Core
  • Reference Design and Technical Documents
  • Nios II HAL Driver (Object Code) and Application Example (C Code)
  • Windows Driver and Application Example (VC++)

Device Utilization and Performance


Getting Started

1. Request an Evaluation version with License from 2. An email send to download the IP Core and the license file to compile the Quartus II design. 3. The IP Core installs documents including tutorial, software guide, reference design, Nios II driver and examples, Windows driver and examples and testing applications. 4. Integrate and test in your design. 5. Reference documents are also available at For any question or support, contact at

IP Quality Metrics

Year IP was first released2005
Latest version of Quartus supported17.0
Altera Customer Use
IP has been successfully implemented in production with at least one customerY

Customer deliverables include the following:

  • Design file (encrypted source code or post-synthesis netlist)
  • Simulation model for ModelSim Altera edition
  • Timing and/or layout constraints
  • Testbench or design example
  • Documentation with revision control
  • Readme file
Any additional customer deliverables provided with IP
Nios II HAL Object Library & Application example, Windows Driver and Application example
Parameterization GUI allowing end user to configure IPY
IP core is enabled for OpenCore Plus SupportY
Source language
Testbench languageVerilog
Software drivers providedY
Driver OS supportWindows, Linux
User InterfaceAvalon-MM
IP-XACT Metadata includedN
Simulators supportedAltera ModelSim
Hardware validated Y. Altera Board Name
Industry standard compliance testing performed
If No, is it planned?Y
IP has undergone interoperability testing
Interoperability reports available  N

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