Supported Device Family:
The USB 2.0 Device, Software Enumeration (USB20SR) IP Core is a RAM based USB 2.0 device core with 32-bit Avalon interface and ULPI interface support. The core supports both High Speed(480 Mbps) and Full Speed(12 Mbps) functionality. The core supports three preconfigured endpoints Control, IN, and OUT. It can be configured for up to 15 IN as well as OUT endpoints on customer's request at additional cost. IP core has been implemented in Verilog HDL and its functionality has been verified using different test cases in simulation environment as well as on hardware. It is provided as Altera Qsys Ready component and hence can be easily integrated in Qsys system. The package includes ModelSim pre-compiled library of Host-BFM with predefined test cases for IP core simulation and verification.
1. Request an Evaluation version with License from http://www.slscorp.com/licensing/ip-licensing.html. 2. An email send to download the IP Core and the license file to compile the Quartus II design. 3. The IP Core installs documents including tutorial, software guide, reference design, Nios II driver and examples, Windows driver and examples and testing applications. 4. Integrate and test in your design. 5. Reference documents are also available at http://www.slscorp.com/downloads/category/113-usb20sr.html For any question or support, contact at email@example.com.
IP Quality Metrics
|Year IP was first released||2005|
|Latest version of Quartus supported||17.0|
|Altera Customer Use|
|IP has been successfully implemented in production with at least one customer||Y|
Customer deliverables include the following:
|Any additional customer deliverables provided with IP||Nios II HAL Object Library & Application example, Windows Driver and Application example|
|Parameterization GUI allowing end user to configure IP||Y|
|IP core is enabled for OpenCore Plus Support||Y|
|Software drivers provided||Y|
|Driver OS support||Windows, Linux|
|IP-XACT Metadata included||N|
|Simulators supported||Altera ModelSim|
|Hardware validated||Y. Altera Board Name http://www.slscorp.com/products/development-boards/corecommander.html|
|Industry standard compliance testing performed||N|
|If No, is it planned?||Y|
|IP has undergone interoperability testing||N|
|Interoperability reports available||N|
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