USB 2.0 Device with FIFO Interface (USB20HF)

Block Diagram

Solution Type: IP Core

End Market: Computer & Storage, Consumer, Industrial, Medical, Military, Test & Measurement, Wireline

Evaluation Method: OpenCore Plus

Technology: Interface Protocols: Communications

Arria Series: Arria 10, Arria V, Arria 10 SoC, Arria V SoC

Cyclone Series: Cyclone IV, Cyclone V, Cyclone V SoC

MAX Series: MAX 10, MAX V

Stratix Series: Stratix IV, Stratix V

Overview

The USB20HF Device IP Core is USB 2.0 device core with FIFO interface for Bulk IN and Bulk OUT endpoints with ULPI interface support. The core supports three pre-configured endpoints Control, Bulk IN, and Bulk OUT. It is Configurable for up to 15 IN/OUT endpoints on customer request on chargeable basis. Each configurable endpoint has an endpoint controller that supports interrupt, bulk, and isochronous transfers. Device controller communicates with the host through FIFO interface of the core. The core supports both HighSpeed (480Mbps) & FullSpeed (12Mbps) functionality. The core has been optimized for Altera FPGAs and its functionality has been verified on the hardware with Altera Quartus II. The package includes ModelSim pre-compiled library for core simulation and verification.

Features

    Device Utilization and Performance

    Refer http://www.slscorp.com/ip-cores/communication/usb-20-device/usb20hf.html

    Getting Started

    1. Request an Evaluation version with License from http://www.slscorp.com/licensing/ip-licensing.html. 2. An email send to download the IP Core and the license file to compile the Quartus II design. 3. The IP Core installs documents including tutorial, software guide, reference design, Nios II driver and examples, Windows driver and examples and testing applications. 4. Integrate and test in your design. 5. Reference documents are also available at http://www.slscorp.com/downloads/category/114-usb20hf.html For any question or support, contact at support@slscorp.com.

    IP Quality Metrics

    Basic
    Year IP was first released2006
    Latest version of Quartus supported17.0
    Altera Customer Use
    IP has been successfully implemented in production with at least one customerY
    Deliverables

    Customer deliverables include the following:

    • Design file (encrypted source code or post-synthesis netlist)
    • Simulation model for ModelSim Altera edition
    • Timing and/or layout constraints
    • Testbench or design example
    • Documentation with revision control
    • Readme file
    Y
    Any additional customer deliverables provided with IP
    Windows Driver and Application Example
    Parameterization GUI allowing end user to configure IPN
    IP core is enabled for OpenCore Plus SupportY
    Source language
    Verilog
    Testbench languageVerilog
    Software drivers providedN
    Driver OS supportWindows, Linux
    Implementation
    User InterfaceOther: FIFO
    IP-XACT Metadata includedN
    Verification
    Simulators supportedAltera ModelSim
    Hardware validated Y. Altera Board Name http://www.slscorp.com/products/development-boards/corecommander.html
    Industry standard compliance testing performed
    N
    If No, is it planned?Y
    Interoperability
    IP has undergone interoperability testing
    N
    Interoperability reports available  N

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