The SLS USB 3.0/3.1 Gen 1 IP Core is the SuperSpeed core that supports connectivity between TI USB 3.0/3.1 Gen 1 PHY (TUSB1310 ) and Altera FPGA. The IP Core is wrapped around with software drivers and examples for its ease of use and quick integration. The ready to use USB 3.0 development board availability makes the integration faster. The IP Core package also contains the reference design that can be used directly for starting a custom application development. The IP Core has been optimized for Altera FPGAs and its functionality has been verified on the hardware with Altera Quartus II software. The package includes ModelSim precompiled library for IP Core simulation and verification.
1. Request an Evaluation version with License from http://www.slscorp.com/licensing/ip-licensing.html. 2. An email send to download the IP Core and the license file to compile the Quartus II design. 3. The IP Core installs documents including tutorial, software guide, reference design, Nios II driver and examples, Windows driver and examples and testing applications. 4. Integrate and test in your design. 5. Reference documents are also available at http://www.slscorp.com/downloads/category/127.html For any question or support, contact at email@example.com.
IP Quality Metrics
|Year IP was first released||2011|
|Latest version of Quartus supported||15.1|
|Altera Customer Use|
|IP has been successfully implemented in production with at least one customer||Y|
Customer deliverables include the following:
|Any additional customer deliverables provided with IP||Nios II HAL Object Library & Application example, Windows Driver and Application example|
|Parameterization GUI allowing end user to configure IP||Y|
|IP core is enabled for OpenCore Plus Support||Y|
|Software drivers provided||Y|
|Driver OS support||Windows, Linux|
|IP-XACT Metadata included||N|
|Simulators supported||Altera ModelSim|
|Hardware validated||Y. Altera Board Name http://www.slscorp.com/products/development-boards/usb-3-0-development-board.html|
|Industry standard compliance testing performed||N|
|If No, is it planned?||Y|
|IP has undergone interoperability testing||N|
|Interoperability reports available||N|
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