USB 3.0/3.1 Gen 1 Device, Software based enumeration FIFO Interface (USB30SF)

Block Diagram

Solution Type: IP Core

End Market: Computer & Storage, Consumer, Industrial, Medical, Military, Test & Measurement, Wireline

Evaluation Method: OpenCore Plus

Technology: Interface Protocols: Communications

Arria Series: Arria 10, Arria V, Arria 10 SoC, Arria V SoC

Cyclone Series: Cyclone IV, Cyclone V, Cyclone V SoC

Stratix Series: Stratix IV, Stratix V

Segments: 

Supported Device Family: 

Solution Type: 

Overview

The SLS USB 3.0/3.1 Gen 1 IP Core is the SuperSpeed core that supports connectivity between TI USB 3.0/3.1 Gen 1 PHY (TUSB1310 ) and Altera FPGA. The IP Core is wrapped around with software drivers and examples for its ease of use and quick integration. The ready to use USB 3.0 development board availability makes the integration faster. The IP Core package also contains the reference design that can be used directly for starting a custom application development. The IP Core has been optimized for Altera FPGAs and its functionality has been verified on the hardware with Altera Quartus II software. The package includes ModelSim precompiled library for IP Core simulation and verification.

Features

  • Supports CONTROL, BULK transfer without stream support, USB2.0 backward compatible
  • Implementation of Link Layer & Protocol Layer, Support 16-bit and 32-bit Phy layer data interface
  • Implements CRC calculation and generation in hardware
  • All Link layer power state handling, Configurable endpoint selection

Device Utilization and Performance

Refer http://www.slscorp.com/ip-cores/communication/usb-30-device/usb-3-0-device-software-based-enumeration-fifo-interface-usb30sf.html

Getting Started

1. Request an Evaluation version with License from http://www.slscorp.com/licensing/ip-licensing.html. 2. An email send to download the IP Core and the license file to compile the Quartus II design. 3. The IP Core installs documents including tutorial, software guide, reference design, Nios II driver and examples, Windows driver and examples and testing applications. 4. Integrate and test in your design. 5. Reference documents are also available at http://www.slscorp.com/downloads/category/127.html For any question or support, contact at support@slscorp.com.

IP Quality Metrics

Basic
Year IP was first released2011
Latest version of Quartus supported17.0
Altera Customer Use
IP has been successfully implemented in production with at least one customerY
Deliverables

Customer deliverables include the following:

  • Design file (encrypted source code or post-synthesis netlist)
  • Simulation model for ModelSim Altera edition
  • Timing and/or layout constraints
  • Testbench or design example
  • Documentation with revision control
  • Readme file
Y
Any additional customer deliverables provided with IP
Nios II HAL Object Library & Application example, Windows Driver and Application example
Parameterization GUI allowing end user to configure IPY
IP core is enabled for OpenCore Plus SupportY
Source language
Verilog
Testbench languageVerilog
Software drivers providedY
Driver OS supportWindows, Linux
Implementation
User InterfaceAvalon-MM
IP-XACT Metadata includedN
Verification
Simulators supportedAltera ModelSim
Hardware validated Y. Altera Board Name http://www.slscorp.com/products/development-boards/usb-3-0-development-board.html
Industry standard compliance testing performed
N
If No, is it planned?Y
Interoperability
IP has undergone interoperability testing
N
Interoperability reports available  N

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