Ethernet MAC & PCS & FEC

Block Diagram

Solution Type: IP Core

End Market: Automotive, Broadcast, Computer & Storage, Consumer, Industrial, Medical, Military, Test & Measurement, Wireless, Wireline

Evaluation Method: Source Code

Technology: Interface Protocols: Ethernet

Arria Series: Arria 10, Arria V, Arria 10 SoC, Arria V SoC

Cyclone Series: Cyclone V, Cyclone V SoC

Stratix Series: Stratix IV, Stratix V

Overview

The Universal Ethernet MAC/PCS offers the industry's lowest latency, power, and size. The highly flexible IP Core can be customized to speeds from 1 Gbps to 400 Gbps

Features

  • 1-400Gbps
  • Lowest latency
  • Smallest gate count
  • Flexible for ease of design

Device Utilization and Performance

Depends on MAC Rate

Getting Started

RTL source code Data sheets Test Benches Bring up guide

IP Quality Metrics

Basic
Year IP was first released2013
Latest version of Quartus supported15.1
Altera Customer Use
IP has been successfully implemented in production with at least one customerY
Deliverables

Customer deliverables include the following:

  • Design file (encrypted source code or post-synthesis netlist)
  • Simulation model for ModelSim Altera edition
  • Timing and/or layout constraints
  • Testbench or design example
  • Documentation with revision control
  • Readme file
N
Parameterization GUI allowing end user to configure IPN
IP core is enabled for OpenCore Plus SupportN
Source language
Verilog
Testbench languageVerilog
Software drivers providedN
Driver OS supportN/A
Implementation
User InterfaceAXI; Avalon-MM
IP-XACT Metadata includedN
Verification
Simulators supportedAll
Hardware validated Y. Altera Board Name Customer HW
Industry standard compliance testing performed
N
If No, is it planned?Y
Interoperability
IP has undergone interoperability testing
Y
Interoperability reports available  N

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