The 5 Mega Pixel Digital Camera Development Package provides everything you need to develop a 5 Mega Pixel Digital Camera on the Terasic FPGA system board. The kit contains hardware design (in Verilog) and software to load the picture taken into the PC and save it as BMP/JPG file. The Getting Started User Guide shows users how to exercise the digital camera functions.
- Support exposure time controlling-Users can adjust the exposure according to the light of the surrounding area
- Support motion capture mode; Software allows users to upload the picture captured into PC & save the picture into bitmap or JPEG for viewing
- Equipped with Micron 5 Mega Pixel CMOS sensor; Support 2592H x 1944V active pixels; Output data in RGB Bayer Pattern format
- Full resolution frame rate up to 15 frame per second (FPS); Programmable controls: gain, frame rate, frame size, exposure; On-chip PLL
- Global reset release; Bulb exposure mode; Snapshot mode to take frames on demand; Horizontal and vertical mirror image; Auto black level calibration
- Complete reference design with source code in Verilog
- Digital camera design demonstration
Board Quality Metrics
|Latest version of Quartus supported||13.0|
|Required Collateral Available|
|Reliability / Quality Assurance|
Defects per Million Opportunities (DPMO)
|Parts per Million (PPM)||N/A|
|Return Material Authorization (RMA) Policy||If you want to make a return, please write an email to us within 7 days after you’ve received the product. The product must be unopened. (If the package is damaged upon receipt, please take photos and inform us immediately.) For more details, please visit: RMA.Terasic.com|
|CE Compliant||N. N/A|
|Conflict Mineral Policy Compliant
|Test Plan Summary|
Reference Designs from System CD for customers to access all the peripherals on board.
|ISO 9000 & 9001
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