ADC-CoC

From Terasic Inc.

Board Image

Block Diagram

Board Category: Development Kit

Components & Interface: Converter: AD; Expansion: Generic; Industry Standard: Ethernet, USB Device

End Market: Automotive, Broadcast, Computer & Storage, Consumer, Industrial, Medical, Military, Test & Measurement, Wireline

Technology: DSP, Embedded Design, General Purpose

Board Feature: General User IO: LED, Push Button, Slider Switch

Cyclone Series: Cyclone V SoC: Cyclone V SE

Overview

The ADC-SoC is a SoC FPGA motherboard with dual-channel high-speed ADC. The main card is based on the Terasic DE0-Nano-SoC board with a built-in high-speed ADC circuit on the DCC (AD / DA Data Conversion Card) on top of the main card. This feature makes the board an ideal platform for systems that require high-speed ADC applications. The built-in ADC circuit uses SMA as the input interface. The circuit provides two channels, each with 14-bit resolution and a sample rate of up to 150 MSPS (Megasamples per Second).

Order Information

Ordering Code
Pricing
Buy
P0435$550.00Buy Now

Development Kit Hardware Contents

  • Cyclone V SoC FPGA with ARM Cortex-A9 Dual-Core; USB Blaster II; Three 50MHz clock sources from the clock generator
  • Arduino Expansion Header (Uno R3 compatibility), can connect with Arduino shields; Two 14-bit AD Converters with 150 MSPS
  • 2 Push Buttons; 4 Slide Switches; 8 Green User LEDs; Three 50MHz Clock Sources from the Clock Generator; A/D Converter, 10-pin Analog input
  • 1 GB DDR3 SDRAM; 1 Gigabit Ethernet PHY with RJ45 connector; USB OTG Port, USB Micro-AB connector; Micro SD Card Socket
  • Accelerometer; UART to USB, USB Mini-B Connector; Warm and Cold Reset Buttons; On-Board RTC; LTC 2x7 Expansion Header

Development Kit Software Contents

  • Schematic and Mechanical Drawing
  • ADC-SoC Control Panel - access various peripherals on the FPGA board from a host computer
  • ADC-SoC System Builder - create a Quartus II project with top-level design file, pin assignments, and I/O standard settings automatically
  • Memory Reference Design

Support Document

File Name
Description
Version
doc-us-dsnbk-42-2608010102169-thdb-hdmi-userguide1-3.pdfADC-SoC User Manual1.0

Board Quality Metrics

Basic
Latest version of Quartus supported 16.1
Required Collateral Available
User Guide Y
Board Schematics Y
Reliability / Quality Assurance

Defects per Million Opportunities (DPMO)

N/A
Parts per Million (PPM)
N/A
Board Policy
Return Material Authorization (RMA) Policy If you want to make a return, please write an email to us within 7 days after you've received the product. The product must be unopened. (If the package is damaged upon receipt, please take photos and inform us immediately.) For more details, please visit: RMA.Terasic.com
Compliance
RoHS Compliant Y
CE Compliant N. N/A
Conflict Mineral Policy Compliant
Y
Test Plan Summary

Reference Designs from System CD for customers to access all the peripherals on board.

Additional Compliance
ISO 9000 & 9001

Design Solutions Network Members provide products and/or services that are sold or licensed by the Member and not Altera or its affiliates. Altera and its affiliates hereby disclaim any express or implied warranty of any kind including warranties of merchantability, noninfringement of intellectual property, or fitness for any particular purpose with respect to any such products and/or services.