Cyclone V SE Device Family - DE1-SoC Board

From Terasic Inc.

Board Image

Block Diagram

Board Category: Development Kit

Components & Interface: Audio: Iomic; Converter: AD; Industry Standard: Ethernet, PS2, USB Device; Video: VGA Output

End Market: Broadcast, Computer & Storage, Consumer, Industrial, Medical, Test & Measurement, Wireline

Technology: Embedded Design

Board Feature: General User IO: 7 Segment Display, LED, Push Button, Slider Switch

Cyclone Series: Cyclone V SoC: Cyclone V SE

Overview

The DE1-SoC Development Kit presents a robust hardware design platform built around the Intel System-on-Chip (SoC) FPGA, which combines the latest dual-core Cortex-A9 embedded cores with industry-leading programmable logic for ultimate design flexibility. Users can now leverage the power of tremendous re-configurability paired with a high-performance, low-power processor system. Intel's SoC integrates an ARM-based hard processor system (HPS) consisting of processor, peripherals and memory interfaces tied seamlessly with the FPGA fabric using a high-bandwidth interconnect backbone. The DE1-SoC development board includes hardware such as high-speed DDR3 memory, video and audio capabilities, Ethernet networking, and much more. The DE1-SOC Development Kit contains all components needed to use the board in conjunction with a computer that runs the Microsoft Windows XP or later (64-bit OS and Quartus II 64-bit are required to compile projects for DE1-SoC).

Order Information

Ordering Code
Pricing
Buy
P0159$249Buy Now

Development Kit Hardware Contents

  • EPCS128 on FPGA; On-Board USB Blaster II;
  • 24-bit VGA DAC; 24-bit CODEC, Line-in, line-out, and microphone-in jacks; TV Decoder and TV-in connector
  • USB to UART; IR Emitter/Receiver; Gig. Ethernet;Two Port USB 2.0 Host
  • 64MB (32Mx16) SDRAM on FPGA; 1GB (2x256Mx16) DDR3 SDRAM on HPS;Micro SD Card Socket on HPS
  • Two 40-pin Expansion Headers; One 10-pin ADC Input Header

Development Kit Software Contents

  • Board Support Package for OpenCL
  • DE1-SoC System Builder - create a Quartus II project with top-level design file, pin assignments, and I/O standard settings automatically.
  • Linux Board Support Package
  • FPGA and HPS Reference Designs
  • Schematic and Mechanical Drawing

Support Document

File Name
Description
Version
doc-us-dsnbk-42-4207350307415-de1-soc-mtl2-user-manual.pdfDE1-SoC User Manual2.0

Board Quality Metrics

Basic
Latest version of Quartus supported 13.1
Required Collateral Available
User Guide Y
Board Schematics Y
Reliability / Quality Assurance

Defects per Million Opportunities (DPMO)

1073
Parts per Million (PPM)
1787
Board Policy
Return Material Authorization (RMA) Policy If you want to make a return, please write an email to us within 7 days after you?ve received the product. The product must be unopened. (If the package is damaged upon receipt, please take photos and inform us immediately.) For more details, please visit: RMA.Terasic.com
Compliance
RoHS Compliant Y
CE Compliant N. N/A
Conflict Mineral Policy Compliant
Y
Test Plan Summary

Reference Designs from System CD for customers to access all the peripherals on board.

Additional Compliance
ISO 9000 & 9001

Design Solutions Network Members provide products and/or services that are sold or licensed by the Member and not Altera or its affiliates. Altera and its affiliates hereby disclaim any express or implied warranty of any kind including warranties of merchantability, noninfringement of intellectual property, or fitness for any particular purpose with respect to any such products and/or services.