The DE10-Nano Development Kit presents a robust hardware design platform built around the Intel System-on-Chip (SoC) FPGA, which combines the latest dual-core Cortex-A9 embedded cores with industry-leading programmable logic for ultimate design flexibility. Users can now leverage the power of tremendous re-configurability paired with a high-performance, low-power processor system. Altera’s SoC integrates an ARM-based hard processor system (HPS) consisting of processor, peripherals and memory interfaces tied seamlessly with the FPGA fabric using a high-bandwidth interconnect backbone. The DE10-Nano development board is equipped with high-speed DDR3 memory, analog to digital capabilities, Ethernet networking, and much more that promise many exciting applications. The DE10-Nano Development Kit contains all the tools needed to use the board in conjunction with a computer that runs the Microsoft Windows XP or later.
- DE10-Nano Control Panel
|doc-us-dsnbk-42-4302081511597-de10-nano-user-manual.pdf||DE10-Nano User Manual||1.0|
Board Quality Metrics
|Latest version of Quartus supported||15.1|
|Required Collateral Available|
|Reliability / Quality Assurance|
Defects per Million Opportunities (DPMO)
|Parts per Million (PPM)||N/A|
|Return Material Authorization (RMA) Policy||If you want to make a return, please write an email to us within 7 days after you’ve received the product. The product must be unopened. (If the package is damaged upon receipt, please take photos and inform us immediately.) For more details, please visit: RMA.Terasic.com|
|CE Compliant||N. N/A|
|Conflict Mineral Policy Compliant
|Test Plan Summary|
Reference Designs from System CD for customers to access all the peripherals on board.
|ISO 9000 & 9001
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