DE1-SoC-MTL2

From Terasic Inc.

Board Image

Block Diagram

Board Category: Development Kit

Components & Interface: Audio: Iomic; Converter: AD; Expansion: Generic; Industry Standard: Ethernet, PS2, USB Device; Video: VGA Output

End Market: Broadcast, Computer & Storage, Consumer, Industrial, Medical, Test & Measurement

Technology: Embedded Design, General Purpose

Board Feature: General User IO: 7 Segment Display, LED, Push Button, Slider Switch

Cyclone Series: Cyclone V SoC: Cyclone V SE

Overview

The DE1-SoC-MTL2 Development Kit is a comprehensive design environment with everything embedded developers need to create processing-based systems. The DE1-SoC-MTL2 delivers an integrated platform including hardware, design tools, and reference designs for developing embedded software and hardware platforms in a wide range of applications. The fully integrated kit allows developers to rapidly customize their processor and IP to best suit their specific application. The DE1-SoC-MTL2 features a DE1-SoC development board targeting Intel Cyclone® V SE SoC FPGA, as well as a capacitive LCD multimedia color touch panel which supports five-point multi-touch and gestures. The all-in-one embedded solution offered on the DE1-SoC-MTL2, in a combination of an LCD touch panel and digital image module, provides embedded developers the ideal platform for multimedia applications with unparallel processing performance. Developers can benefit from the use of FPGA-based embedded processing system such as mitigating design risk and obsolescence, design reuse, lowering bill of material (BOM) costs by integrating powerful graphics engines within the FPGA. For SoC reference design in Linux for touch-screen display, please refer to the DE1-SoC-MTL2 Control Panel.

Order Information

Ordering Code
Pricing
Buy
K0159$405Buy Now

Development Kit Hardware Contents

  • 85K LEs; Dual Core ARM Cortex-A9 (HPS); EPCS128; On-Board USB Blaster II; 64MB SDRAM for FPGA; 1GB DDR3 SDRAM for HPS; MicroSD Card Socket
  • Two USB 2.0 Port; UART to USB; 10/100/1000 Ethernet; PS/2; IR Emitter/Receiver; I2C Multiplexer
  • 24-bit CODEC, 24-bit VGA DAC; TV Decoder and TV-in Connector; AdC; G-Sensor on HPS
  • 5 User Keys; 10 User Switches; 11 User LEDs; 2 HPS Reset Buttons; Six 7-Segment Displays
  • G-Sensors on HPS; 7-inch 800*480 TFT LCD; 8-bit RGB; 5-point Multi-Touch; Gesture Supports

Development Kit Software Contents

  • Linux, Android and OpenCL BSP (Board Support Package)
  • FPGA and HPS Reference Designs
  • DE1-SoC System Builder - create a Quartus II Project with top-level design file, pin assignments, and I/O standard settings automatically
  • Schematic and Mechanical Drawing
  • Memory Design

Support Document

File Name
Description
Version
doc-us-dsnbk-42-4207350307415-de1-soc-mtl2-user-manual.pdfDE1-SoC-MTL2 User Manual1.0

Board Quality Metrics

Basic
Latest version of Quartus supported 14.0
Required Collateral Available
User Guide Y
Board Schematics Y
Reliability / Quality Assurance

Defects per Million Opportunities (DPMO)

N/A
Parts per Million (PPM)
N/A
Board Policy
Return Material Authorization (RMA) Policy If you want to make a return, please write an email to Terasic within 7 days after you've received the product. The product package must be unopened. (If the package is damaged upon receipt, please take photos and informed Terasic immediately. For more details, please visit: RMA.Terasic.com
Compliance
RoHS Compliant Y
CE Compliant N. N/A
Conflict Mineral Policy Compliant
Y
Test Plan Summary

Reference Designs from System CD for Customers to access all the peripherals on board.

Additional Compliance
ISO 9000 & 9001

Design Solutions Network Members provide products and/or services that are sold or licensed by the Member and not Altera or its affiliates. Altera and its affiliates hereby disclaim any express or implied warranty of any kind including warranties of merchantability, noninfringement of intellectual property, or fitness for any particular purpose with respect to any such products and/or services.