TR5 FPGA development kit using the Altera Stratix V GX FPGA provides high-speed operation and transmission with large capacity up to 952K LE. The board provides four FMC connectors and a 2x20 GPIO connector. It offers a total of more than 500 I/Os for users to expand the usage with the peripherals connected. There are built-in high-speed DDR3 memory and SSRAM to increase the bandwidth for accessing large amounts of data for high-speed computation. In addition, the board also has PCIe and SATA interfaces for high-speed data transmission. The main applications of TR5 are ASIC prototyping validation and the establishment of prototype systems. The FMC connectors onboard are standard interfaces. Users can purchase or develop various FMC daughter cards to expand their system. For developers who need to use multiple FPGAs, they can leverage Terasic’s FMC or PCIe cable to establish an inter-stackable multi-boards communication system. Users can also purchase Terasic PCIe daughter card to communicate with host PC. The TR5 development kit includes a variety of reference design examples for peripherals such as DDR3 SDRAM, SD card, USB-to-UART, SATA, PCIe, and an FMC connector. The kit is user friendly and enables users to quickly get started or verify the functions. The kit also provides a tool named "System Builder" software. It can automatically generate a complete Quartus project including pin assignment and clock configuration IP upon users' selections of peripherals, FMC daughter cards, and a designated clock frequency. It helps users avoid time-consuming and error-prone manual pin-assignment work.
- With 952K LEs to meet all kinds of complex designs
- Four VITA FMC connectors that contribute up to 495 FPGA free user I/Os
- Hign Bandwidth data transfer with an elastic expansion of various interfaces
- PCIeX4 connector to process board to board to PC connection to transfer data
- 8GB DDR3 SO-DIMM provides high-speed and efficient memory bandwidth for up to 800 MHz
- TR5 System Builder
- Schematic and Mechanical Drawing
- Flash and Oscillator Programming
- Memory & PCIe Reference Design
|doc-us-dsnbk-42-3711010203004-tr5-user-manual.pdf||TR5 User Manual||1.0|
Board Quality Metrics
|Latest version of Quartus supported||15.1|
|Required Collateral Available|
|Reliability / Quality Assurance|
Defects per Million Opportunities (DPMO)
|Parts per Million (PPM)||N/A|
|Return Material Authorization (RMA) Policy||If you want to make a return, please write an email to us within 7 days after you've received the product. The product must be unopened. (If the package is damaged upon receipt, please take photos and inform us immediately.) For more details, please visit: RMA.Terasic.com|
|CE Compliant||N. N/A|
|Conflict Mineral Policy Compliant
|Test Plan Summary|
Reference Designs from System CD for customers to access all the peripherals on board.
|ISO 9000 & 9001
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