TR10a-HL Arria 10 FPGA Development Kit

From Terasic Inc.

Board Image

Block Diagram

Board Category: COTS, Development Kit

Components & Interface: Expansion: Generic; Industry Standard: PCIE Edge

End Market: Broadcast, Computer & Storage, Consumer, Industrial, Medical, Military, Test & Measurement, Wireless

Technology: ASIC Prototyping, DSP, Embedded Design, General Purpose, Interface Protocols

Board Feature: General User IO: Dip Rocker Switch, LED, Push Button, Rotary Dial Selector

Arria Series: Arria 10: Arria 10 GX

Overview

The Terasic TR10a-HL Arria 10 GX FPGA Development Kit provides the ideal hardware solution for designs that demand high capacity and bandwidth memory interfacing, ultra-low latency communication, and power efficiency. With a full-height, 1/2-length form-factor package, the TR10a-HL is designed for the most demanding high-end applications, empowered with the top-of-the-line Altera Arria 10 GX, delivering the best system-level integration and flexibility in the industry. The Arria® 10 GX FPGA features integrated transceivers that transfer at a maximum of 12.5 Gbps, allowing the TR10a-HL to be fully compliant with version 3.0 of the PCI Express standard, as well as allowing an ultra low-latency, straight connections to four external 40G QSFP+ modules. Not relying on an external PHY will accelerate mainstream development of network applications enabling customers to deploy designs for a broad range of high-speed connectivity applications. For designs that demand high capacity and high speed for memory and storage, the TR10a-HL delivers with six independent banks of QDRII+ SRAM, high-speed parallel flash memory. The feature-set of the TR10a-HL fully supports all high-intensity applications such as low-latency trading, cloud computing, high-performance computing, data acquisition, network processing, and signal processing.

Order Information

Ordering Code
Pricing
Buy
P0497$5520Buy Now

Development Kit Hardware Contents

  • 1150K Les; On-Board USB Blaster II or JTAG Header for FPGA programming
  • Four QSFP+ Connectors; 8 PCI Express Edge Connectors (includes Windows PCIe drivers)
  • Six Independent 550 MHz QDRII+SRAMs, 18-bits Data Bus and 72Mbit for each
  • 50 MHz Oscillator; Programmable Clock Generator
  • Temperature Sensor; Power Monitor; Fan Control;One RS422 Expansion Header;

Development Kit Software Contents

  • TR10a-HL System Builder
  • Schematic and Mechanical Drawing
  • Memory & PCIe Reference Design
  • Flash and Oscillator Programing

Support Document

File Name
Description
Version
doc-us-dsnbk-42-5703181507555-tr10a-hl-user-manual.pdfTR10a-HL1

Board Quality Metrics

Basic
Latest version of Quartus supported 15.1
Required Collateral Available
User Guide Y
Board Schematics Y
Reliability / Quality Assurance

Defects per Million Opportunities (DPMO)

N/A
Parts per Million (PPM)
N/A
Board Policy
Return Material Authorization (RMA) Policy If you want to make a return, please write an email to us within 7 days after you’ve received the product. The product must be unopened. (If the package is damaged upon receipt, please take photos and inform us immediately.) For more details, please visit: RMA.Terasic.com
Compliance
RoHS Compliant Y
CE Compliant N. N/A
Conflict Mineral Policy Compliant
Y
Test Plan Summary

Reference Designs from System CD for customers to access all the peripherals on board.

Additional Compliance
ISO 9000 & 9001

Design Solutions Network Members provide products and/or services that are sold or licensed by the Member and not Altera or its affiliates. Altera and its affiliates hereby disclaim any express or implied warranty of any kind including warranties of merchantability, noninfringement of intellectual property, or fitness for any particular purpose with respect to any such products and/or services.