CDC-200/300 Customizable Display Controllers

Block Diagram

Solution Type: IP Core

End Market: Automotive, Broadcast, Computer & Storage, Consumer, Industrial, Medical, Military, Test & Measurement

Evaluation Method: OpenCore Plus

Technology: DSP: Video and Image Processing

Arria Series: Arria 10, Arria V, Arria 10 SoC, Arria V SoC

Cyclone Series: Cyclone IV, Cyclone V, Cyclone V SoC

MAX Series: MAX 10

Stratix Series: Stratix IV, Stratix V

Overview

CDC-200 and CDC-300 (http://tes-dst.com/tes-dst/index.php/graphics-rendering/cdc-200-300?innerpage_style=1) are fully Customizable Display Controller IPs supporting the OpenWF display API specification. A number of features can be configured both at synthesis time and at run time. In this way the display controller can be adapted for e.g. systems with limited features targeting special applications or for an generic feature set with more flexibility. At compile time, the most important configuration options are input formats, number of layers, alpha blending technique and (for CDC-300) the scaling option. The maximum number of input layers only depends on the bus bandwidth and timing constraints. CDC-200/300 can support AMBA APB and AHB/AXI as well as the Altera AVALON bus interface. The controller provides a digital RGB signal with video data and signals for horizontal/vertical blank and synchronization as output.

Features

    Device Utilization and Performance

    LE count depends on configuration, starting at ~1k LEs for one layer

    Getting Started

    CDC-200/300 is included in the free of charge eval kits of the D/AVE cores: http://tes-dst.com/tes-dst/index.php/graphics-rendering/cdc-200-300?innerpage_style=1 (Registration required)

    IP Quality Metrics

    Basic
    Year IP was first released2011
    Latest version of Quartus supported13.1
    Altera Customer Use
    IP has been successfully implemented in production with at least one customerY
    Deliverables

    Customer deliverables include the following:

    • Design file (encrypted source code or post-synthesis netlist)
    • Simulation model for ModelSim Altera edition
    • Timing and/or layout constraints
    • Testbench or design example
    • Documentation with revision control
    • Readme file
    Y
    Any additional customer deliverables provided with IP
    Sample driver and example programs
    Parameterization GUI allowing end user to configure IPY
    IP core is enabled for OpenCore Plus SupportY
    Source language
    VHDL
    Testbench languageVHDL
    Software drivers providedY
    Driver OS supportbare metal, Linux
    Implementation
    User InterfaceAXI; Avalon-MM; Other: AMBA APB
    IP-XACT Metadata includedN
    Verification
    Simulators supportedModeltech ModelSim, Cadence NCSim
    Hardware validated Y. Altera Board Name NEEK, VEEK-MT, VEEK-MT C5 SoC
    Industry standard compliance testing performed
    Y
    If yes, which test(s)?Spyglass, Cadence HAL
    If yes, on which Altera device(s)?CIII, CIV, CV
    If Yes, date performed
    09/30/2011
    Interoperability
    IP has undergone interoperability testing
    Y
    Interoperability reports available  N

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