D/AVE 2D

Block Diagram

Solution Type: IP Core

End Market: Automotive, Broadcast, Computer & Storage, Consumer, Industrial, Medical, Military, Test & Measurement

Evaluation Method: OpenCore Plus

Technology: DSP: Video and Image Processing

Arria Series: Arria 10, Arria V, Arria 10 SoC, Arria V SoC

Cyclone Series: Cyclone IV, Cyclone V, Cyclone V SoC

MAX Series: MAX 10

Stratix Series: Stratix IV, Stratix V

Overview

D/AVE 2D (http://tes-dst.com/tes-dst/index.php/graphics-rendering/dave-2d?innerpage_style=1) is a Hardware IP Core, optimized for easy integration into FPGAs and ASICs. Focus of D/AVE 2D is to provide cost efficient high quality vector graphics with subpixel processing and an extended anti-aliasing functionality. D/AVE 2D has been developed for all applications that benefit from high quality vector graphics. Examples are navigation, dashboard and OSDs in the automotive and aviation area as well as modern Smart-Phone like HMIs in consumer, test&measurement and industrial applications.

Features

    Device Utilization and Performance

    D/AVE 2D: 10k LEs D/AVE 2D-Lite: 6k LEs (at about 2.5 times lower performance than D/AVE 2D)

    Getting Started

    Complete evaluation kit is available free of charge at http://tes-dst.com/tes-dst/index.php/graphics-rendering/dave-2d?innerpage_style=1 (Registration required).

    IP Quality Metrics

    Basic
    Year IP was first released2007
    Latest version of Quartus supported13.1
    Altera Customer Use
    IP has been successfully implemented in production with at least one customerY
    Deliverables

    Customer deliverables include the following:

    • Design file (encrypted source code or post-synthesis netlist)
    • Simulation model for ModelSim Altera edition
    • Timing and/or layout constraints
    • Testbench or design example
    • Documentation with revision control
    • Readme file
    Y
    Any additional customer deliverables provided with IP
    SoftDAVE (Pixel exact emulator for Windows PCs), Drivers and example programs
    Parameterization GUI allowing end user to configure IPY
    IP core is enabled for OpenCore Plus SupportY
    Source language
    VHDL
    Testbench languageVHDL
    Software drivers providedY
    Driver OS supportbare metal, Linux
    Implementation
    User InterfaceAXI; Avalon-MM
    IP-XACT Metadata includedN
    Verification
    Simulators supportedModeltech ModelSim, Cadence NCSim
    Hardware validated Y. Altera Board Name NEEK, VEEK-MT, VEEK-MT C5 SoC
    Industry standard compliance testing performed
    Y
    If yes, which test(s)?Spyglass, Cadence HAL
    If yes, on which Altera device(s)?CIII, CIV, CV
    If Yes, date performed
    06/01/2007
    Interoperability
    IP has undergone interoperability testing
    Y
    Interoperability reports available  N

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