D/AVE HD

Block Diagram

Solution Type: IP Core

End Market: Automotive, Broadcast, Computer & Storage, Consumer, Industrial, Medical, Military, Test & Measurement

Evaluation Method: OpenCore Plus

Technology: DSP: Video and Image Processing

Arria Series: Arria 10, Arria V, Arria 10 SoC, Arria V SoC

Cyclone Series: Cyclone IV, Cyclone V, Cyclone V SoC

Stratix Series: Stratix IV, Stratix V

Overview

D/AVE HD (http://tes-dst.com/tes-dst/index.php/graphics-rendering/dave-hd?innerpage_style=1) is an evolution in the D/AVE family supporting high quality 2D rendering and basic 3D rendering for displays up to 4K x 4K. Targeting modern graphics applications on high resolution displays in the industrial, test&measurement, medical, military, avionics, automotive and consumer markets, D/AVE HD is designed to be fast with powerful functionality and at the same time optimized regarding size and footprint. D/AVE HD is available for both FPGA and ASIC integration with high customizability as well as scalability and a peak performance between 1 and 16 pixels per clock cycle. D/AVE HD offers several enhancements over the previous D/AVE 2D version as related to various blit operations, cache enhancements, texture pre-fetch, power management and system functionality.

Features

    Device Utilization and Performance

    50k LEs fully featured 30k LEs without OpenVG support (option) Performance up to 16 pixels per cycle. Typically 4 times faster than D/AVE 2D

    Getting Started

    Complete evaluation kit is available free of charge at http://tes-dst.com/tes-dst/index.php/graphics-rendering/dave-hd?innerpage_style=1 (Registration required)

    IP Quality Metrics

    Basic
    Year IP was first released2012
    Latest version of Quartus supported13.1
    Altera Customer Use
    IP has been successfully implemented in production with at least one customerN
    Deliverables

    Customer deliverables include the following:

    • Design file (encrypted source code or post-synthesis netlist)
    • Simulation model for ModelSim Altera edition
    • Timing and/or layout constraints
    • Testbench or design example
    • Documentation with revision control
    • Readme file
    Y
    Any additional customer deliverables provided with IP
    SoftDAVE (Pixel exact emulator for Windows PCs), Drivers and example programs
    Parameterization GUI allowing end user to configure IPY
    IP core is enabled for OpenCore Plus SupportY
    Source language
    VHDL
    Testbench languageVHDL
    Software drivers providedY
    Driver OS supportbare metal, Linux
    Implementation
    User InterfaceAXI; Avalon-MM
    IP-XACT Metadata includedN
    Verification
    Simulators supportedModeltech ModelSim, Cadence NCSim
    Hardware validated Y. Altera Board Name VEEK-MT, VEEK-MT C5 SoC
    Industry standard compliance testing performed
    Y
    If yes, which test(s)?Spyglass, Cadence HAL
    If yes, on which Altera device(s)?CIV, CV SoC
    If Yes, date performed
    12/03/2012
    Interoperability
    IP has undergone interoperability testing
    N
    Interoperability reports available  N

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