HMI System Solution: Guiliani + D/AVE 2D + CDC-200

Block Diagram

Solution Type: IP Core

End Market: Automotive, Broadcast, Computer & Storage, Consumer, Industrial, Medical, Military, Test & Measurement

Evaluation Method: OpenCore Plus

Technology: DSP: Video and Image Processing

Arria Series: Arria 10, Arria V, Arria 10 SoC, Arria V SoC

Cyclone Series: Cyclone IV, Cyclone V, Cyclone V SoC

MAX Series: MAX 10

Stratix Series: Stratix IV, Stratix V

Overview

Driven by smart phones customers expect Smart HMIs on all kind of devices: Modern graphical control elements (widgets) combined with smooth animations on high-resolution touch-screen displays replace single-color segment displays and hard-keys. A reliable touch screen performance combined with an intuitive GUI design is a must. With the combination of the Guiliani HMI Framework, the D/AVE 2D graphics rendering core and the CDC-200 display controller, TES offers a ready-to-use, low-footprint and thus cost efficient solution for Smart HMIs on Altera FPGAs and SoCs: http://tes-dst.com/tes-dst/index.php/hmi-tooling/guiliani--dave-2d-for-altera-fpgas?innerpage_style=1

Features

    Device Utilization and Performance

    <20 kLEs (including bus system, memory interfaces etc), ~12k LEs of this for D/AVE 2D an CDC-200 Program Memory (Guiliani + D/AVE drivers) : ~2.5MB on NIOS II

    Getting Started

    Free-of-charge demo and eval kits are available for download at http://www.tes-dst.com/support/index.php/support-home/download-eval-kits/guiliani (registration required). The Guiliani SDK and complete documentation can be found at www. guiliani.de/en.

    IP Quality Metrics

    Basic
    Year IP was first released2012
    Latest version of Quartus supported13.1
    Altera Customer Use
    IP has been successfully implemented in production with at least one customerY
    Deliverables

    Customer deliverables include the following:

    • Design file (encrypted source code or post-synthesis netlist)
    • Simulation model for ModelSim Altera edition
    • Timing and/or layout constraints
    • Testbench or design example
    • Documentation with revision control
    • Readme file
    Y
    Any additional customer deliverables provided with IP
    Guiliani SDK and PC Editor, example HMI project including source code
    Parameterization GUI allowing end user to configure IPY
    IP core is enabled for OpenCore Plus SupportY
    Source language
    VHDL
    Testbench languageVHDL
    Software drivers providedY
    Driver OS supportbare metal, Linux
    Implementation
    User InterfaceAXI; Avalon-MM
    IP-XACT Metadata includedN
    Verification
    Simulators supportedModeltech ModelSim, Cadence NCSim
    Hardware validated Y. Altera Board Name NEEK, VEEK-MT, VEEK-MT C5 SoC
    Industry standard compliance testing performed
    Y
    If yes, which test(s)?Spyglass, Cadence HAL
    If yes, on which Altera device(s)?CIII, CIV, CV
    If Yes, date performed
    10/01/2012
    Interoperability
    IP has undergone interoperability testing
    Y
    Interoperability reports available  N

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