Warping Engine

Block Diagram

Solution Type: IP Core

End Market: Automotive, Broadcast, Computer & Storage, Consumer, Industrial, Medical, Military, Test & Measurement

Evaluation Method: OpenCore Plus

Technology: DSP: Video and Image Processing

Arria Series: Arria 10, Arria V, Arria V SoC

Cyclone Series: Cyclone IV, Cyclone V, Cyclone V SoC

MAX Series: MAX 10

Stratix Series: Stratix IV, Stratix V


TES Warping Engine (http://tes-dst.com/tes-dst/index.php/graphics-rendering/warping-engine?innerpage_style=1) is a specialized IP core for arbitrary high-performance re-mapping of bitmaps from memory to memory. Applications are for example pre-warping for projection on head-up displays or fisheye-correction of camera images. The IP core adapts to different bus interfaces like AMBA APB and AHB/AXI as well as the Altera Avalon bus interface at different bus width (e.g. 32, 64, 128 bits).


    Device Utilization and Performance

    ~7k LEs

    Getting Started

    The Warping Engine is included in the free-of-charge TES D/AVE HD evaluation kit: http://tes-dst.com/tes-dst/index.php/graphics-rendering/warping-engine?innerpage_style=1 (registration required).

    IP Quality Metrics

    Year IP was first released2013
    Latest version of Quartus supported13.1
    Altera Customer Use
    IP has been successfully implemented in production with at least one customerN

    Customer deliverables include the following:

    • Design file (encrypted source code or post-synthesis netlist)
    • Simulation model for ModelSim Altera edition
    • Timing and/or layout constraints
    • Testbench or design example
    • Documentation with revision control
    • Readme file
    Any additional customer deliverables provided with IP
    Tool to generate Look Up Table and example source code
    Parameterization GUI allowing end user to configure IPY
    IP core is enabled for OpenCore Plus SupportY
    Source language
    Testbench languageVHDL
    Software drivers providedY
    Driver OS supportbare metal, Linux
    User InterfaceAXI; Avalon-MM
    IP-XACT Metadata includedN
    Simulators supportedModeltech ModelSim, Cadence NCSim
    Hardware validated Y. Altera Board Name VEEK-MT, VEEK-MT C5 SoC
    Industry standard compliance testing performed
    If No, is it planned?Y
    IP has undergone interoperability testing
    Interoperability reports available  N

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