The UDPSDR-HF1 features a 14-bit ADC sampling at 80Msps. The HF1 is designed to be a front-end companion to the Altera BeMicroSDK from Arrow Electronics. Together, the HF1 and BeMicroSDK form a complete 100kHz – 30MHz Digital Down Conversion receiver. The UDPSDR-HF1 joins the high-performance UDPSDR-HF2 (email@example.comMsps) receiver and the UDPSDR-TX2 transmitter (14-bits@210Msps) to round out the SDRstick family.
- BeMicroSDK FPGA image for HDSDR, HPSDR, SDR# and GNU Radio
|doc-us-dsnbk-29-3104342205-udpsdr-hf1-users-manual-v1-1.pdf||UDPSDR-HF1 Users Manual||1.1|
Board Quality Metrics
|Latest version of Quartus supported||15.1|
|Required Collateral Available|
|Reliability / Quality Assurance|
Defects per Million Opportunities (DPMO)
|Parts per Million (PPM)||0|
|Return Material Authorization (RMA) Policy||Contact firstname.lastname@example.org for RMA. All returns require RMA.|
|CE Compliant||N. Should be CE compliant, but not tested.This is a piece of test equipment.|
|Conflict Mineral Policy Compliant
|Test Plan Summary|
FPGA load for BeMIcroSDK to implement functional 100kHz - 30 MHz receiver. \nBeRadio FPGA source code for BeMicroSDK to build stand-alone MW radio (requires some code modifications).
|ISO 9000 & 9001
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