Dsp Floating Point

New digital signal processing (DSP) systems use floating-point solutions to achieve a high degree of numeric stability and dynamic range. Applications such as radar, advanced wireless antenna processing and medical imaging require floating-point capabilities in FPGAs and SoCs. As DSP applications grow in size and capability, FPGAs and SoCs offer the highest performing platforms available for any floating-point DSP implementation.

At 14 nm, Stratix® 10 FPGAs and SoCs deliver the industry's highest floating-point performance with up to 10 tera floating point operations per second (TFLOPS) performance. Find out more about our Stratix 10 FGPA and SoC DSP capabilities.

At 20 nm, Arria® 10 FPGAs and SoCs deliver the industry’s first devices with hardened floating-point operators delivering up to 1.5 TFLOPs performance. Find out more about our Arria 10 FPGA and SoC variable-precision DSP block architecture.

Latest News: New Support for Intel® SoC FPGAs (and associated floating-point implementation) with the Latest MathWorks R2014b Release

HDL Coder and Embedded Coder offer new support for the Intel SoC FPGA family with MathWorks R2014b. Developers familiar with MathWorks tools have the added convenience of staying in this development environment for code generation targeted for Intel SoC FPGAs.

FPGA designers and processor programmers will now share a common design methodology streamlined for targeting of Intel SoC FPGAs.

For further information, visit https://www.mathworks.com/hardware-support/altera-soc-ecoder.html.

Get started on our floating-point DSP solutions with these white papers and webcasts.

White Papers

Understanding Peak Floating-Point Performance Claims

This white paper calculates and compares the peak floating-point performance of digital signal processors, graphics processing units (GPUs), and FPGAs. Find out how Intel can reliably claim up to 1.5 TFLOPS of performance in Arria 10 devices and 10 TFLOPs in Stratix 10 devices using an industry-standard method, and compare this claim against the claims of another FPGA vendor.

Read white paper (PDF)

Enabling Impactful DSP Designs on FPGAs with Hardened Floating-Point Implementation.

Looking to learn more about Intel's hardened floating-point implementation? This white paper discusses the novel architecture, beginning with Arria 10 devices and continuing through Stratix 10 devices, that will enable the highest floating-point DSP algorithmic performance in FPGAs to-date.

Read white paper (PDF)

Read white paper

BDTI evaluates energy efficiency of real-world, complex DSP designs on Intel FPGA 28 nm development boards:

  • Power benchmarks for complex DSP designs: Cholesky and QR-based matrix factorization
  • Results and usability of the floating-point tool flow

Read white paper (PDF)

Read white paper

BDTI evaluates performance of real-world, complex DSP designs on Intel FPGA 28 nm development boards:

  • Performance benchmarks for complex DSP designs: Cholesky and QR-based matrix factorization
  • Results and usability of the floating-point tool flow

Read white paper (PDF)
Watch preview

Webcasts

View Video

NEW: View now, On-Demand, 15 minutes

Accelerating Design Development Time with Hard Floating-Point DSP Blocks in FPGAs

Watch this webcast to get:

  • An overview of current floating-point implementation challenges
  • An introduction to Intel's hard floating-point DSP blocks
  • An overview of how you can achieve unprecedented DSP performance, designer productivity, and logic efficiency
View Video

View now, On-Demand, 30 minutes

Implementing Floating-Point DSP in an FPGA

Watch this webcast to:

  • Learn how Intel FPGAs solve floating-point challenges
  • See Intel's model-based tool flow using our DSP Builder Advanced Blockset and MATLAB and Simulink tools from MathWorks
  • Get a third-party white paper from BDTI that analyzes our floating-point DSP design flow

Intel and MathWorks Joint Partnership

Introduction to FPGA Design Using MATLAB and Simulink

Learn how many companies are reducing FPGA design cycle time by 33-50% or more by adopting workflows based on MATLAB and Simulink.

Watch webcast

Designing and Developing Pulse Doppler Radars Using FPGAs

Learn how radar system engineers can reduce the time required to model, simulate, and implement radar system designs and their constituent signal processing algorithms.

Watch webcast