• Floating-Point DSP Blocks
  • Variable-Precision DSP
  • Advantages

Altera revolutionized the digital signal processing (DSP) blocks in its Generation 10 FPGAs and SoCs to provide the industry’s first hardened floating-point DSP blocks.

Three DSP block modes available in Arria 10 and Stratix 10 FPGAs and SoCs

  • Floating-point mode (Hardened IEEE 754 operators)
  • Standard-precision mode (18-bit fixed-point multipliers)
  • High-precision mode (27-bit fixed-point multipliers)


Altera's variable-precision DSP architecture with hardened floating-point operators integrated in its Generation 10 FPGAs and SoCs provide several benefits, including:

  • Shortened development time by 6-12 months
  • Improved performance with up to 10 TFLOPS of DSP performance
  • Significantly higher resource efficiency, with improved power and resource usage 

What's New for DSP in Altera Quartus® Prime Software v15.1 Release

  • DSP Builder design interface improvements
    • New dynamic finite impulse response (FIR) filter option
    • New unified control or signals block interfaces
    • New option to generate Karatsuba complex multipliers (reducing resources used in fixed point
    • Avalon® interface improvements
  • Four new Forward Error Correction IP MegaCore intellectual properties (IPs) (High-Speed Reed-Solomon, BCH, LDPC, Turbo)
  • New floating-point complex multiplier megafunction

Key Benefits

Shortened Development Time

Using FPGAs with native floating-point operators eliminates the need to convert your floating-point designs to fixed-point designs, an already challenging and lengthy task. The productivity advantages of not having to convert to fixed-point design are further amplified as you iterate your design.

Improved Floating-Point Performance

Past floating-point implementations were limited in performance due to timing bottlenecks by additional logic and routing resources required to implement floating-point operators. With native support for floating point in the new variable-precision digital signal processing (DSP) blocks, floating-point operations can run at the frequency of the DSP blocks, delivering significantly higher performance.

Higher Resource Efficiency

Because past floating-point implementations required additional logic and routing resources, large complex floating-point designs would run out of logic before DSP blocks. DSP blocks with hardened floating point allow designers to fully utilize all floating-point operators in all of the DSP blocks while lowering power and enabling more logic to be available for additional features and functions.

For more information:

Industry's First DSP Block with Hard Floating-Point Operators

Altera has revolutionized their DSP blocks to provide the industry’s first DSP block with native support for IEEE 754 single-precision floating point in dedicated hardened circuitry. This technological breakthrough allows the variable-precision DSP blocks to be configured at compile time into the IEEE 754 floating-point, standard-precision (18 bit), or high-precision (27 bit) mode. In floating-point mode, each DSP block provides a single-precision multiplier and single-precision adder, enabling DSP designers with the following key benefits:

  • Shortened development time by 6-12 months
  • Improved performance, with up to 10 tera floating-point operations per second (TFLOPS) of DSP performance with Arria 10 devices
  • Significantly higher resource efficiency, improving power and resource usage

To learn more, check out these new resources:

View Video Webcast: Accelerating Design Development Time with Hard Floating-Point DSP Blocks in FPGAs
Learn how you can achieve unprecedented DSP performance, designer productivity, and logic efficiency using the hard floating-point DSP blocks in Arria 10 and Stratix 10 devices.
Read White Paper

White Paper: Understanding Peak Floating-Point Performance Claims
Calculate and compare the peak floating-point performance of digital signal processors, graphics processing units (GPUs), and FPGAs. Find out how Altera can reliably claim up to 1.5 TFLOPS of performance in Arria 10 devices and 10 TFLOPS in Stratix 10 devices using an industry-standard method, and compare this claim against the claims of another FPGA vendor before making your design choice.

Read White Paper

White Paper: Enabling Impactful DSP Designs on FPGAs with Hardened Floating-Point Implementation

Looking to learn more about Altera's hardened floating-point implementation? This white paper discusses the novel architecture, beginning with Arria 10 devices and continuing through Stratix 10 devices, that will enable the highest floating-point DSP algorithmic performance in FPGAs to-date.