Altera revolutionized the digital signal processing (DSP) blocks in its Generation 10 FPGAs and SoCs to provide the industry’s first hardened floating-point DSP blocks.
What's New for DSP in Altera Quartus II Software v14.1 Release
DSP Builder v14.1 and Quartus® II software deliver new DSP support. (For more information on Open Computing Language (OpenCLTM), visit www.altera.com/opencl)
- IEEE 754-compliant hard floating-point models for basic and complex math.h functions (accessible via DSP Builder, megafunctions, and MegaCore® intellectual properties (IPs)
- Updated reference designs to demonstrate hard floating-point functionality
- Support for multichannel arithmetic logic unit (ALU) folding
- Automated System-in-the-Loop functionality
Shortened Development Time
Using FPGAs with native floating-point operators eliminates the need to convert your floating-point designs to fixed point, an already challenging and lengthy task. The productivity advantages of not having to convert to fixed point are further amplified as you iterate your design.
Improved Floating-Point Performance
Past floating-point implementations were limited in performance due to timing bottlenecks by additional logic and routing resources required to implement floating-point operators. With native support for floating point in the new variable-precision DSP blocks, floating-point operations can run at the frequency of the DSP blocks, delivering significantly higher performance.
Higher Resource Efficiency
Because past floating-point implementations required additional logic and routing resources, large complex floating-point designs would run out of logic before DSP blocks. DSP blocks with hardened floating point allow designers to fully utilize all floating-point operators in all of the DSP blocks while lowering power and enabling more logic to be available for additional features and functions.
For more information:
Industry's First DSP Block with Hard Floating-Point Operators
Altera has revolutionized their digital signal processing (DSP) blocks to provide the industry’s first DSP block with native support for IEEE 754 single-precision floating point in dedicated hardened circuitry. This technological breakthrough allows the variable-precision DSP blocks to be configured at compile time into the IEEE 754 floating-point, standard-precision (18 bit), or high-precision (27 bit) mode. In floating-point mode, each DSP block provides a single-precision multiplier and single-precision adder, enabling DSP designers with the following key benefits:
- Shortened development time by 6-12 months
- Improved performance, with up to 1.5 tera floating point operations per second (TFLOPS) of DSP performance with Arria® 10 devices
- Significantly higher resource efficiency, improving power and resource usage
To learn more, check out these new resources:
|Webcast: Accelerating Design Development Time with Hard Floating-Point DSP Blocks in FPGAs
Learn how you can achieve unprecedented DSP performance, designer productivity, and logic efficiency using the hard floating-point DSP blocks in Arria 10 and Stratix® 10 devices.
White Paper: Understanding Peak Floating-Point Performance Claims