Leveraging Intel® Stratix® 10 or Arria® 10 devices, Hybrid Memory Cube (HMC) will deliver significant advantages over solutions using conventional DRAM technology which makes it an ideal solution for next generation high performance computing, military, and wireline communication applications.
Intel’s Generation 10 HMC solution promises to deliver significant advantages over solutions using conventional SDRAM technology.
- TSMC 20 nm process
- 15% higher performance than current high-end devices
- 40% lower mid-range power
- Up to 96 transceiver channels
- 28 Gbps chip-to-chip
- 1.9 times processor systems improvement
- Intel 14 nm Tri-gate process
- 2X performance increase
- Up to 70% power savings
- 144 transceiver channels
- 30 Gbps chip-to-chip
- Quad core A53 processor from ARM
- 3D capability for integrating SRAM, DRAM, and ASIC
Flexible, Highest Performance, and Lowest Risk Solution
Intel extends its HMC technology leadership with the production-ready HMC Controller IP core and Arria 10 support at 10, 12.5, and 15Gbps. Talk to your Intel FPGA Sales Representative about our 15 Gbps Hybrid Memory Cube Controller IP support.
Read our white paper Addressing Next-Generation Memory Requirements Using Altera FPGAs and HMC Technology to learn about the advantages of using serial memory solutions to break the memory barrier.
The successful interoperability demonstration between Intel Stratix V FPGAs and Micron’s HMC allows system designers to start exploring use models for this revolutionary technology today. HMC is the long awaited answer to limitations of conventional memory technology, providing up to 15 times the bandwidth while using 70 percent less energy and 90 percent less space than existing technologies. System Designers can start evaluating HMC benefits today with the confidence that full production support will be available with Intel’s Generation 10 portfolio.
Watch Video: Accelerating System Bandwidth with Serial Memory Solutions Using Intel FPGAs and Hybrid Memory Cube Technology
Intel: Statix V 5SGXA3 FPGAs
Micron: HMC device
Interoperability Configuration Set Up
XCVR data rate = 10 Gbps
Data packets, 16B, 32B, 64B, and 128B data packets (power of two payload schemes)
Exercise four HMC links
The HMC is a revolutionary, next generation DRAM technology that promises to address some of the major challenges faced by system designers. The HMC combines the best of logic and DRAM processes into a single heterogeneous package using 3D Through Silicon Via (TSV) technology to stack multiple DRAM layers over a base logic layer. The DRAM layers handle data only, while the logic layer handles all control within the HMC. The HMC technology specification has been developed by the Hybrid Memory Cube Consortium (HMCC). Intel is one of the leading consortium members and has been collaborating with Micron Technology in defining the HMC interface specification and carrying out system-level interoperability testing. The HMC specification was ratified by the consortium in April 2013.
The HMC uses a transceiver-based interface which supports up to four serial links. Each link is built using 16 full duplex transceiver channels, resulting in up to a total of 64 channels for the interface. Each link can run at data rates ranging from 10, 12.5, 15 Gbps providing up to 1 Tbps of raw aggregated interface bandwidth in each direction.