HiGig / HiGig+ / HiGig 2

Broadcom HiGigTM and HiGig+TM protocols use an enhanced XAUI PHY, and tag each packet with a 12-byte HiGig header. HiGig+ extends the XAUI PHY line rate from 3.125 Gbps up to 3.75 Gbps per lane. HiGig 2 extends the XAUI PHY line rate to 6.375 Gbps.  The motivation for using the enhanced XAUI PHY for these protocols is to add switching functionality, such as quality of service (QoS), port trunking, mirroring across devices, and link aggregation, which is not available with standard XAUI.  

Intel® devices that are compliant with the requirements of HiGig and HiGig+ include:

  • Arria® 10 FPGAs
  • Stratix® V GT FPGAs (up to 4 channels at rates up to 28.05 Gbps and 32 channels at rates up to 12.5 Gbps)
  • Stratix V GX FPGAs (up to 66 channels at rates up to 14.1 Gbps)
  • Stratix V GS FPGAs (up to 48 channels at rates 14.1 Gbps)
  • Stratix IV GX FPGAs (up to 32 channels at rates up to 8.5 Gbps, and up to 16 additional channels at rates up to 3.2 Gbps)
  • Stratix IV GT FPGAs (up to 24 channels at rates up to 11.3 Gbps, and up to 24 additional channels at rates up to 6.375 Gbps)
  • Stratix II GX FPGAs (up to 20 channels at rates up to 6.375 Gbps)
  • Arria II GX FPGAs (up to 16 channels at rates up to 3.75 Gbps)

You can use these devices to implement any interface based on XAUI, HiGig, or HiGig+.

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