Interlaken and Interlaken Look-Aside are scalable, chip-to-chip interconnect protocols designed to enable transmission speeds from 10 to 300 Gbps and beyond. Using the latest transceiver technology and a flexible protocol layer, Intel® FPGA Interlaken and Interlaken Look-Aside intellectual property (IP) cores provide excellent performance and productivity needed for emerging applications that are requiring significant scalability and integration onto a single FPGA. Technical differentiation for these attributes is realized by combining the benefits of Intel FPGA silicon and the Interlaken and Interlaken Look-Aside IP cores. Both IP cores feature a unique balance of soft and hard logic IP to enable such integration and scalability without the additional silicon costs. By providing this integrated balance, maximum flexibility and performance can be achieved.
With the release of Intel's next-generation Intel Arria® 10 FPGAs and SoCs, the Intel FPGA Interlaken IP Portfolio accomplishes major development milestones: third-generation soft IP (includes media access control (MAC) and second-generation hardened IP (includes physical coding sublayer (PCS) / physical medium attachment (PMA). These seasoned, battle-tested cores continue to provide the additional robustness and maturity required for new, more intelligent systems.
Intel FPGA Interlaken IP core is ideal for multi-terabit routers and switches for access, carrier Ethernet and data center applications that demand IP configurability to optimize for various traffic profiles, and scalability for next-generation platforms.
The Interlaken IP core is Interlaken Protocol Definition v1.2 compliant and allows system developers to achieve high bandwidth throughput in their systems. This pre-built, ready-go-go building block IP shortens customer's design cycle resulting in faster time to market.
Intel FPGA Interlaken Look-Aside IP core is suited for coprocessing packet classification typically used for networking applications which include quality of service routing, traffic profiling, and firewall functions. The IP's low-latency packet interface, coupled with its efficient data processing capability, enables high degree of design scalability for emerging network applications.
The Interlaken Look-Aside IP core is Interlaken Look-Aside Protocol Definition v1.1 compliant and allows system developers to eliminate the computational bottlenecks associated with older, packet classification methods.
Information and Contact Details
For Interlaken or Interlaken Look-Aside IP inquiries, please contact your local Intel FPGA sales representative.
- Intel® Stratix® 10 FPGAs and SoCs
- Intel Arria 10 FPGAs and SoCs
- Stratix® V FPGAs
- Arria V FPGAs
- Stratix® IV FPGAs