Interlaken and Interlaken Look-Aside are scalable, chip-to-chip interconnect protocols designed to enable transmission speeds from 10 to 300 Gbps and beyond. Using the latest transceiver technology and a flexible protocol layer, Intel® FPGA Interlaken and Interlaken Look-Aside intellectual property (IP) cores provide the best performance and productivity needed for emerging applications that are requiring significant scalability and integration on to a single FPGA. Technical differentiation for these attributes is realized by combining the benefits of Intel FPGA silicon and the Interlaken and Interlaken Look-Aside IP cores. Both IP cores feature a unique balance of soft and hard logic IP to enable such integration and scalability without the additional silicon costs. By providing this integrated balance, maximum flexibility and performance can be achieved.
With the release of Intel's next-generation Intel Arria® 10 FPGAs and SoCs, the Intel FPGA Interlaken IP Portfolio accomplishes major development milestones: third-generation soft IP (includes media access control (MAC)) and second-generation hardened IP (includes physical coding sublayer (PCS) / physical medium attachment (PMA)). These seasoned, battle-tested cores continue to provide the additional robustness and maturity required for new, more intelligent systems.