Title
Application Notes
AN 768: Multi Rate (Up to 12G) SDI II Reference Design for Arria 10 Devices
AN 761: Board Management Controller
AN 762: Battery Management System Reference Design
AN 759: Arria 10 SoC Secure Boot User Guide

AN 737: SEU Detection and Recovery in Arria 10 Devices

Arria 10 SEU Detection and Recovery Reference Design Files

AN 757: 1G/2.5G Ethernet Design Examples

AN 757 Design Example Files

AN 687: Implementing QPI Using the Transceiver Native PHY IP Core in Stratix V Devices
AN 756: Altera GPIO to Altera PHYLite Design Implementing Guidelines

AN 755: Implementing JESD204B IP Core System Reference Design with ARM HPS As Control Unit (Baremetal Flow)

AN 755 Reference Design Files

AN 754: MIPI D-PHY Solution with Passive Resistor Networks in Altera Low Cost FPGA
AN 753: Altera JESD204B IP Core and ADI AD6676 Hardware Checkout Report
AN 752: Guidelines for Handling Altera Wafer Level Chip Scale Package
AN 749: Altera JESD204B IP Core and ADI AD9144 Hardware Checkout Report
AN 747: Altera PHYLite for Parallel Interfaces Loopback Reference Designs Application Note
AN742: PMBus SmartVID Controller Reference Designs
AN727: EPCS to EPCQ Migration Guideline
AN750: Using the Altera PDN Tool to Optimize Your Power Delivery Network Design
AN746: Triple Rate SDI II Reference Designs for Arria 10 Devices

AN744: Scalable Triple Speed Ethernet Reference Designs for Arria 10 Devices

AN744 Reference Design Files (With IEEE 1588v2 Feature)

AN744 Reference Design Files (Without IEEE 1588v2 Feature)

AN741: Remote System Upgrade for MAX 10 FPGA Devices over UART with the Nios II Processor
AN748: Nios II Gen2 Migration Guide
AN459: Guidelines for Developing a Nios II HAL Device Driver

AN739 Altera 1588 System Solution

AN739 Reference Design Image File

AN739 Reference Design Files

AN736 Nios II Processor Booting from Altera Serial Flash (EPCQ)
AN 735: Altera Low Latency Ethernet 10G MAC IP Core Migration Guidelines
AN 729: Implementing JESD204B IP Core System Reference Design with Nios II Processor As Control Unit 
AN 729 Reference Design Files (32 MB)
AN711: Power Reduction Features in Arria 10 Devices
AN 709: HPS SoC Boot Guide - Cyclone V SoC Development Kit

AN 699 Using the Altera Ethernet Design Toolkit

AN 699 Reference Design Files

AN 693: Remote Hardware Debugging over TCP/IP for Altera SoC
LINUX drivers for AN693 (49 KB)
AN 692: Power Sequencing Considerations for Arria 10 Devices
AN661: Implementing Fractional PLL Reconfiguration with Altera PLL and Altera PLL Reconfig Megafunctions 
merge_mif.tcl (4 KB) 
PLL_DynamicPhaseShift.qar (88 KB) 
PLL_MIFstreaming.qar (67 KB) 
PLL_Reconfig_DPS.qar (48 KB) 
PLL_Reconfig_MNC.qar (48 KB) 
PLL_Reconfig_Qsys.qar (746 KB) 
PLL Reconfiguration Calculator (30 KB)
AN 556: Using the Design Security Features in Altera FPGAs 
AN 556 Design Files (7 KB)
AN 539: Test Methodology of Error Detection and Recovery using CRC in Altera FPGA Devices  
AN539 Design Example (425 KB) 
AN539 Design Example 2 (234 KB)
Use of MLCC Capacitors
EP53XXXUI QFN Package Soldering Guideline
EP53XXXQI QFN Package Soldering Guideline
EP53F8QI QFN Package Soldering Guideline
Enpirion EP53F8QI 1.5A Synchronous DCDC Converter Module Evaluation Board
Enpirion EP5358xUI DC/DC Converter Module Evaluation Board
EN6337QI QFN Package Soldering Guideline
Enpirion EN6337QI/EN6347QI DC-DC Converter w/Integrated Inductor Evaluation Board
Startup and Shutdown Sequencing With EN2340/60/90/F0QI Family Synchronous Buck with Integrated Inductor
EN23F0QI QFN Package Soldering Guideline
Enpirion EN23F0QI DC-DC Converter w/Integrated Inductor Evaluation Board
EN2390QI QFN Package Soldering Guideline
Enpirion EN2390QI DC-DC Converter w/Integrated Inductor Evaluation Board
EN2360QI QFN Package Soldering Guideline
Enpirion EN2360QI DC-DC Converter w/Integrated Inductor Evaluation Board
EN2340QI QFN Package Soldering Guideline
Enpirion EN2340QI DC-DC Converter w/Integrated Inductor Evaluation Board
Compensating with High Output Capacitance
AN 734: Cyclone V SoC Power Optimization
AN 733: Altera JESD204B IP Core and TI ADC12J4000 Hardware Checkout Report
AN 731: SSN Guidelines for Cyclone III and Cyclone IV Devices Single-ended Clock Input and I/O Restrictions
AN730:Nios II Processor Booting Methods in MAX 10 Devices
AN 728: I/O PLL Reconfiguration and Dynamic Phase Shift for Arria 10 Devices
AN723: Serial Digital Interface (SDI) II Implementation in Arria 10 Devices
Design Example for AN723 (5 MB)
AN 720: Simulating the ASMI Block in Your Design
AN 719: Altera JESD204B IP Core and TI DAC37J84 Hardware Checkout Report
AN 717: Nios II Gen2 Hardware Development Tutorial
AN 712: Altera JESD204B IP Core and ADI AD9625 Hardware Checkout Report
AN 710: Altera JESD204B IP Core and ADI AD9680 Hardware Checkout Report
AN708: PCI Express DMA Reference Design Using External DDR3 Memory for Stratix V and Arria V GZ Devices
AN 706: Mapping HPS IP Peripheral Signals to the FPGA Interface
AN 705: Scalable 10G Ethernet MAC using 1G/10G PHY
Scalable Multispeed 10G Ethernet MAC using 1G/10G PHY without IEEE 1588v2
Scalable Multispeed 10G Ethernet MAC using 1G/10G PHY with IEEE 1588v2  
AN704: FPGA-based Safety Separation Design Flow for Rapid IEC
AN738: Arria 10 Device Design Guidelines
AN 702: Interfacing a USB PHY to the Hard Processor System USB 2.0 OTG Controller
AN 701: Scalable Low Latency Ethernet 10G MAC using Arria 10 1G/10G PHY
ll-ethernet-10g-a10-phy-lineside.tar.gz
ll-ethernet-10g-a10-phy-lineside-1588.tar.gz  
AN 696: Using the JESD204B MegaCore Function in Arria V Devices
Altera JESD204B MegaCore Function and ADI AD9250 Hardware Checkout Report (1 MB) 
AN 696 Reference Design Example (3 MB)
AN 690: PCI Express Avalon-MM DMA Reference Design
AN 689: High Speed Channel Design Using the SFF-8431 Protocol
AN 684: Design Guidelines for 100 Gbps - CFP2 Interface
AN 681: Stratix V GT Device Design Guidelines
High-Speed Link Tuning Using Signal Conditioning Circuitry in Stratix V Transceivers
AN 678 Reference Design Files (1 MB)
AN 677: Adding New Design Components to the PROFINET IP
AN 676: Using the Transceiver Reconfiguration Controller for Dynamic Reconfiguration in Arria V and Cyclone V Devices
AN 676 Reference Design Example (1 MB)
AN 675: PROFINET Reference Design Bootstrap and Flash Access
AN 674: PROFINET IRT and Getting Started with The Siemens CPU 315 PLC
AN 672: Transceiver Link Design Guidelines for High-Gbps Data Rate Transmission
AN 671: Stratix V Dynamic Transmitter PMA Control for PCI Express
AN 670: Thermal Solutions to Address Height Variation in Stratix V Packages
AN669: Drive-On-Chip Reference Design
AN 668: Serial Digital Interface Reference Design for Stratix V GX and Arria V GX Devices
Arria V GX Design Files (2 MB) 
Stratix V GX Design Files (1 MB)
AN 667: High-Definition Video Reference Design (UDX5)
(The UDX5 reference design improves on the UDX4 reference design by including the latest Deinterlacer II and Scaler II video intellectual property (IP) cores, which are part of the Video and Image Processing Suite.)
AN 664: Using the Stratix V Reconfiguration Controller to Perform Dynamic Reconfiguration
Stratix V Reconfiguration Design Example (1 MB)
AN 662: Arria V and Cyclone V Design Guidelines
AN659: Thermal Management and Mechanical Handling for Lidless Flip Chip Ball-Grid Array
(This application note provides guidance on thermal management and mechanical handling of lidless flip chip ball-grid array (FCBGA) for Altera devices. )
AN 658: Best Design Practices for HardCopy Devices
AN657: Thermal Management and Mechanical Handling for Altera TCFCBGA Devices
AN656: Combining Multiple Configuration Schemes
AN653: Implementing the CPRI Protocol using the Deterministic Latency Transceiver PHY IP Core
an653_Reference_Design_File (346 KB)
AN 652: Arria V Timing Optimization Guidelines
AN 651: PCB Breakout Routing for High-Density Serial Channel Designs Beyond 10 Gbps
AN650: Initializing the UniPHY Nios II Sequencer in HardCopy Devices using FPP Configuration Scheme
an650_UniPHY_HCX_Migration_Reference_Design.zip (2 MB)
AN 649: Design Guidelines for HardCopy IV GX Devices
AN648: Multioutput Scaler Reference Design

AN647: Single-Port Triple-Speed Ethernet and On-Board PHY Chip Reference Design

TSE Single Port SGMII Arria 10 GX

TSE Single Port RGMII Arria V GX
TSE Single Port RGMII Cyclone V GX
TSE Single Port SGMII Stratix V GX
TSE Single Port SGMII Stratix IV GX

AN646: 4K Format Conversion Reference Design
AN 645: Dynamic Reconfiguration of PMA Controls in Stratix V Devices
PMA Controls Reconfiguration Reference Design (14 MB)
AN 644: Migration Between Stratix V GX and Stratix V GT Devices
AN 642: 2.5G Reed-Solomon II MegaCore Function Reference Design
AN 641: Serial Digital Interface Reference Design for Cyclone IV Devices
Design Files for AN 641 (1 MB)
AN639: Inferring Stratix V DSP Blocks for FIR Filtering Applications
AN 638: 10-Gbps Ethernet MAC and XAUI PHY Interoperability Hardware Demonstration Reference Design
AN638 Reference Design for Linux (7 MB) 
AN638 Reference Design for Windows (7 MB)
AN 637: Sharing External Memory Bandwidth Using the Multi-Port Front-End Reference Design
Design Files for AN 637 (18 MB)
AN636: Using Differential I/O Standards in MAX V Devices
AN 635: Implementing SATA and SAS Protocols in Altera Devices
AN 634: PHY IP Design Flow with Interlaken for Stratix V Devices
Interlaken Phy Reference Design (194 KB)
AN 633: Implementing Loopback in Triple-Speed Ethernet Designs With LVDS I/O and GX Transceivers
TSE Loopback Reference Design ArriaII GX (7 MB) 
TSE Loopback Reference Design Stratix IV (6 MB)
AN 631: Replacing Serial EEPROMs with User Flash Memory in Altera MAX Series
AN 630: Real-Time ISP and ISP Clamp for Altera MAX Series
AN 629: Understanding Timing in Altera CPLDs
AN 628: Using the Agilent 3070 Tester for In-System Programming in Altera CPLDs
AN 625: Stratix V Device Design Guidelines
AN624: Debugging with System Console Over TCP/IP
AN 623: Using the DSP Builder Advanced Blockset to Implement Resampling Filters
AN617: RapidIO Dynamic Data Rate Reconfiguration Reference Design for Stratix IV GX Devices
Design Files for AN 617 (2 MB)
AN 613: PCB Stackup Design Considerations for Altera FPGAs
AN 612: Decision Feedback Equalization in Stratix IV Devices
Reference Design for Application Note 612 (969 KB)
AN 611: Mapping 3G-SDI Level B and Dual Link HD-SDI (SMPTE372) Reference Design
Design Files for AN611 (839 KB)
AN 610: Implementing Deterministic Latency for CPRI and OBSAI Protocols in Altera Devices
AN 609: Implementing Dynamic Reconfiguration in Cyclone IV GX Devices
AN 608: HST Jitter and BER Estimator Tool for Stratix IV GX and GT Devices
AN 607: Dynamic Reconfiguration of Transceiver Channels Using Multiple PLLs in Stratix IV Devices
Simulation.zip (102 KB)
AN 606: POS-PHY Level 4 (SPI-4.2) Loopback Reference Design
ModelSim Files (1 MB) 
Design File for AN606 (Stratix III) (2 MB) 
Design File for AN606 (Stratix IV) (2 MB)
AN 605: Using the On-Chip Signal Quality Monitoring Circuitry (EyeQ) Feature in Stratix IV Transceivers
Stratix IV GX Board EyeQ Reference Design (1 MB)
AN 603: Active Serial Remote System Upgrade Reference Design
AN603 Design Files (1 MB)
AN 602: Understanding the Pre-Emphasis and Linear Equalization Features in Stratix IV GX Devices
AN 601: Serial Digital Interface Reference Design for Arria II GX Devices
Design Files for AN 601 (1 MB)
AN 600: Serial Digital Interface Reference Design for Stratix IV Devices
Design Files for AN 600 (Verilog) (763 KB) 
Design Files for AN 600 (VHDL) (728 KB)
AN599: Arria II GX RapidIO Interoperability with TI 6488 DSP Reference Design
AN 597: Getting Started Flow for Board Designs
AN 596: Modeling and Design Considerations for 10 Gbps Connectors
an596_stateye_examples.zip (120 KB)
AN 595: Vectored Interrupt Controller Usage and Applications
Example Designs for AN595 (503 KB)
AN 593: Anti-Tamper Protection for Cyclone III LS Devices
AN 592: Cyclone IV Design Guidelines
AN 589: Using the Design Security Feature in Cyclone III LS Devices
AN 588: 10-Gbps Ethernet Hardware Demonstration Reference Design
AN587: DPRIO and Multiple Instances SDI Application
AN 586: Porting the Jam STAPL and Jam STAPL Byte-Code Players to an Embedded System
AN585: Simulation Debugging Using Triple Speed Ethernet Testbench
AN585: Test Cases (3 MB)
AN 584: Timing Closure Methodology for Advanced FPGA Designs
AN 584: Design Examples (380 KB)
AN 583: Designing Power Isolation Filters with Ferrite Beads for Altera FPGAs
AN 583: VCC to VCCDPLL Spice Examples (159 KB)
AN 581: High Definition Video Reference Design (V2)
AN 580: Achieving Timing Closure in Basic (PMA Direct) Functional Mode
AN580_scripts.zip (17 KB)
AN 578: Manual Placement of CMU PLLs and ATX PLLs in Stratix IV GX and GT Devices
AN 577: Recommended Protocol Configurations for Stratix IV GX FPGAs
AN 574: Printed Circuit Board (PCB) Power Delivery Network (PDN) Design Methodology
AN 573: Implementing the Interlaken Protocol in Stratix IV Transceivers
(Not applicable when designing with Stratix IV GX and Stratix IV GT engineering sample devices)
AN 572: Implementing the Scalable SERDES Framer Interface (SFI-S) Protocol in Stratix IV GT Devices
(Not applicable when designing with Stratix IV GT engineering sample devices)
AN 571: Implementing the SERDES Framer Interface Level 5 (SFI-5.1) Protocol in Stratix IV Devices
AN 570: Implementing the 40G/100G Ethernet Protocol in Stratix IV Devices
(Not applicable when designing with Stratix IV GT engineering sample devices)
AN 569: SDI Flywheel Video Decoder Reference Design
RapidIO Interoperability with TI 6488 DSP Reference Design
(AN568: RapidIO Interoperability with TI 6488 DSP Reference Design)
AN 563: Design Guidelines for Arria II Devices
AN561: Stratix II GX 10GbE Loopback Reference Design
AN 559: High Definition Video Reference Design (V1)
AN 558: Implementing Dynamic Reconfiguration in Arria II Devices
AN557: Stratix III to Stratix IV E Cross-Family Migration Guidelines
AN 554: How to Read HardCopy PrimeTime Timing Reports
AN 553: Debugging Transceivers
AN 553: Design Files (874 KB)
AN 550: Using the DLL Phase Offset Feature in Stratix FPGAs and HardCopy ASICs
altmemphy_ext_dll.zip (48 KB) 
altmemphy_int_dll.zip (47 KB) 
static_dll.zip (18 KB)
AN 549: Managing Designs with Multiple FPGAs
AN 548: Nios II Compact Configuration System for Cyclone III
Design Files for AN 548 (597 KB)
AN 547: Putting Altera MAX Series in Hibernation Mode Using User Flash Memory
Design Example for MAX II (87 KB)
AN 545: Design Guidelines and Timing Closure Techniques for HardCopy ASICs
Example_design.zip (578 KB)
AN 544: Digital IF Modem Design with the DSP Builder Advanced Blockset
AN543: Debugging Nios II Software Using the Lauterbach Debugger
Example Design for AN543 (6 MB)
AN 542: High Definition Video Monitoring Reference Design (M5)
AN 541: SerialLite II Hardware Debugging Guide
AN 540: Nios II MPU Usage
Design Files for AN 540 (221 KB)
AN 537: Implementing UNH-IOL Test Suite Compliance in Arria GX and Stratix II GX Gigabit Ethernet Designs
carrier_detect_logic.zip (2 KB)
AN 536: Design Guidelines for Preparing HardCopy II ASICs
AN 532: An SOPC Builder PCI Express Design with GUI Interface
Design Files for AN 532 (5 MB)
AN 531: Reducing Power with Hardware Accelerators
Design Files for AN 531 (1 MB)
AN 530: Optimizing Impedence Discontinuity Caused by Surface Mount Pads for High-Speed Channel Designs
AN 529: Via Optimization Techniques for High-Speed Channel Designs
AN 528: PCB Dielectric Material Selection and Fiber Weave Effect on High-Speed Channel Routing
AN527: Implementing an LCD Controller
AN 526: 3GPP UMTS Turbo Reference Design
AN 524: High Definition Video Monitoring Reference Design (M4)
AN523: Cyclone III Configuration Interface Guidelines with EPCS Devices
AN 522: Implementing Bus LVDS Interface in Supported Altera Device Families
Design Examples for AN 522 (37 KB)
AN 521: Cyclone III Active Parallel Remote System Upgrade Reference Design
AN521 Design Files (1 MB)
AN 519: Stratix IV Design Guidelines
AN 518: SGMII Interface Implementation Using Soft-CDR Mode of Altera FPGAs
AN 515: 24K FFT for 3GPP LTE RACH Detection
AN 514: Power Optimization in Stratix IV FPGAs
AN 513: RapidIO Interoperability With TI 6482 DSP Reference Design
AN 512: Using the Design Security Feature in Stratix III Devices
AN 511: Polyphase Modulation Using a FPGA for High-Speed Applications
AN 509: Multiplexing SDIO Devices Using Altera MAX Series 
Design Example for MAX II (721 KB)
AN 508: Cyclone III Simultaneous Switching Noise (SSN) Design Guidelines
AN 507: Implementing PLL Reconfiguration in Cyclone III Devices
Design Example 1: an507_de1_display.zip (204 KB) 
Design Example 2: an507_de2_dynphase.zip (84 KB)
AN 506: QR Matrix Decomposition
AN 505: 3GPP LTE Turbo Reference Design
AN 504: DSP System Design in Stratix III Devices
Design Example 1: Parallel FIR (79 KB) 
Design Example 2: Multi-Channel FIR (20 KB) 
Design Example 3: MAC_FIR (vhdl) (21 KB) 
Design Example 4: Large Mult_Add (11 KB)
AN 503: Implementing OFDM Modulation for Wireless Communications
AN 502: Implementing SMBus Controller in Altera MAX Series 
Design Example for MAX II (2 MB)
AN 501: Pulse Width Modulation Using Altera MAX Series 
Design Example for MAX II (279 KB)
AN 500: NAND Flash Memory Interface with Altera MAX Series
Design Example for MAX II (187 KB)
AN 499: Mobile SDRAM Interface Using MAX II CPLDs
AN 499 Design Example (450 KB)
AN 498: LED Blink Using Power Sequencing in Altera MAX Series
Design Example for MAX II (168 KB)
AN 497: LCD Controller Using MAX II CPLDs
AN 497 Design Example (2 MB)
AN 496: Using the Internal Oscillator in Altera MAX Series
Design Example for MAX II (230 KB) 
Design Example for MAX V (257 KB)
AN 495: IDE/ATA Controller Using Altera MAX Series
Design Example for MAX II (418 KB)
AN 494: GPIO Pin Expansion Using I2C Bus Interface in Altera MAX Series 
Design Example for MAX II (273 KB)
AN 493: I2C Battery Gauge Interface Using Altera MAX Series
Design Example for MAX II (465 KB)
AN 492: CF+ Interface Using Altera MAX Series
Design Example for MAX II (346 KB)
AN 491: Auto Start Using Altera MAX Series
Design Example for MAX II (245 KB)
AN 490: Altera MAX Series as Voltage Level Shifters
Design Example for MAX II (147 KB)
AN 489: Using the UFM in MAX II Devices
AN 489 Design Example (551 KB)
AN 488: Stepper Motor Controller Using Altera MAX Series
Design Example for MAX II (350 KB)
AN 487: SPI to I2S Using MAX II CPLDs
AN 487 Desgin Example (589 KB)
AN 486: SPI to I2C Using Altera MAX Series
Design Example for MAX II (385 KB)
AN 485: Serial Peripheral Interface Master in Altera MAX Series
Design Example for MAX II (305 KB)
AN 484: SMBus for GPIO Pin Expansion in MAX II CPLDs
AN 484 Design Example (2 MB)
AN 483: Triple Speed Ethernet Data Path Reference Design 
AN 482: High Definition Video Monitoring Reference Design (M2)
AN 479: Design Guidelines for Implementing LVDS Interfaces in Cyclone Series Devices
AN 478: Using FPGA-Based Parallel Flash Loader with the Quartus II Software
AN 477: Designing RGMII Interface with FPGA and HardCopy Devices
AN 476: Impact of I/O Settings on Signal Integrity in Stratix III Devices
AN 475: Crest Factor Reduction for OFDMA Systems
AN 474: Implementing Stratix III and Stratix IV Programmable I/O Delay Settings in the Quartus II Software
AN 472: Stratix II GX SSN Design Guidelines
AN 471: High-Performance FPGA PLL Analysis with TimeQuest
AN 469: Stratix III Design Guidelines
AN 466: Cyclone III Design Guidelines
AN 465: Implementing OCT Calibration in Stratix III Devices
Design Example 1 (200 KB) 
Design Example 2 (74 KB) 
Design Example 3 (211 KB) 
Stratix III OCT Power Up Example (46 KB)
AN 464: DFT/IDFT Reference Design
AN 462: Implementing Multiple Memory Interfaces Using the ALTMEMPHY Megafunction
Example Design for AN 462: top.qar (715 KB)
AN 461: Design Guidelines for Implementing QDRII+ and QDRII SRAM Interfaces in Stratix III and Stratix IV Devices
Design Example for AN 461 (3 MB)
AN 459: Guidelines for Developing a Nios II HAL Device Driver
AN458: Alternative Nios II Boot Methods
AN458 design example files (36 KB)
AN 457: Integrating Uplink Desubchannelization and Ranging Modules for WiMAX
AN 456: PCI Express High Performance Reference Design
AN 455: Understanding CIC Compensation Filters
AN 454: Implementing PLL Reconfiguration in Stratix III and Stratix IV Devices
Design Examples 1 (413 KB) 
Design Examples 2 (236 KB)
AN 453: HardCopy II Fitting Techniques
AN 451: Downlink Subchannelization for WiMAX
AN 450: Uplink Desubchannelization for WiMAX
AN 449: External Memory Interface Design Guidelines for Stratix II, Stratix II GX, and Arria GX Devices
AN 448: Stratix III Power Management Design Guide
AN 447: Interfacing Altera Devices with 3.3/3.0/2.5 V LVTTL/LVCMOS I/O Systems
AN 446: Debugging Nios II Systems with the SignalTap II Embedded Logic Analyzer
signal_tap_test software file (9 KB)
AN 443: External PHY Support in PCI Express MegaCore Functions
AN 442: Tool Flow for Design of Digital IF for Wireless Systems
Accelerating Nios II Networking Applications
AN 439: Constellation Mapper and Demapper for WiMAX
AN 437: Power Optimization in Stratix III FPGAs
AN 433: Constraining and Analyzing Source-Synchronous Interfaces
AN 432: Using Different PLL Settings Between Stratix II and HardCopy II Devices
AN 431: PCI Express to External Memory Reference Design
AN 429: Remote Configuration Over Ethernet with the Nios II Processor
Application Note 429 Design Files (3 MB)
AN 428: MAX II CPLD Design Guidelines
AN 426: Using MAX II CPLDs as Analog Keyboard Encoders
AN 425: Using the Command-Line Jam STAPL Solution for Device Programming
AN 424: I/O Simulations Using HSPICE
AN 423: Configuring the MicroBlaster Passive Serial Software Driver
Source Code (149 KB)
AN 422: Power Management in Portable Systems Using MAX II CPLDs
AN 421: Accelerating WiMAX DUC & DDC System Designs
WiMAX DUC & DDC Reference Design Web Page (9 KB)
AN 418: SRunner: An Embedded Solution for Serial Configuration Device Programming
Source Code (254 KB)
AN 417: Accelerating Functions with the C2H Compiler: Scatter-Gather DMA with Checksum
Scatter-Gather DMA Design Files (6 KB)
AN 415: DDR and DDR2 SDRAM ECC Reference Design
ECC Reference Design Files (242 bytes)
AN 414: The JRunner Software Driver: An Embedded Solution for PLD JTAG Configuration
Source Code (221 KB)
AN 411: Understanding PLL Timing for Stratix II Devices
Design Example 1 (279 KB) 
Design Example 2 (233 KB)
AN 410: MAX II ISP Update with I/O Control & Register Data Retention
ISP SRAM Download Design Files (11 KB)
AN 409: Design Example Using the altlvds Megafunction & the External PLL Option in Stratix II Devices
Design Example (7 MB)
AN 407: Automotive Audio Reference Design
AN 404: FFT/IFFT Block Floating Point Scaling
AN 400: SMBus Interface for the User Flash Memory in MAX II Devices
SMBus (Read/Write/Erase) Design Files (8 KB) 
SMBus (Read Only) Design Files (8 KB)
AN 396: Crest Factor Reduction
AN 392: Implementing Multiple Legacy DDR/DDR2 SDRAM Controller Interfaces
three controller example (26 KB) 
two controller example (15 KB)
AN 391: Profiling Nios II Systems
AN 387: Upgrading a FIR Compiler v3.1.x Design to v3.2.x
AN 385: Using Stratix GX Transceivers for PCI Express
AN 384: Using Calibrated Series On-Chip Termination in Stratix II Devices
User-Mode Calibration Reference Design (Quartus II Version 4.2 SP1) (233 KB) 
User-Mode Calibration Reference Design (Quartus II Version 5.0) (233 KB)
AN 383: Cyclone II DDR2 SDRAM Demonstration
AN 380: Test DDR or DDR2 SDRAM Interfaces on Hardware Using the Example Driver
AN 379: Active Serial Memory Interface Controller Reference Design
Design Files (11 KB)
AN 376: Cyclone II Filtering Lab
AN 375: Cyclone II FFT Co-Processor Reference Design
AN 373: Avalon Video Input Module
AN 372: Avalon LCD Controller
AN 371: Automotive Graphics System Reference Design
AN 370: Using the Serial Flash Loader With the Quartus II Software
AN 367: Implementing PLL Reconfiguration in Stratix II Devices
Example 1: altpll_reconfig Design with the MIF (244 KB) 
Example 2: altpll_reconfig Design with Write Parameters (249 KB) 
Example 3: altpll_reconfig Design for Phase Shift Stepping (251 KB)
AN 366: Understanding I/O Output Timing for Altera Devices
AN 362: Stratix II Filtering Lab
AN 361: Interfacing DDR & DDR2 SDRAM With Cyclone II Devices
AN 359: POS-PHY Level 4 MegaCore Function Parameter Selection Calculator
Parameter Selection Calculator (2 MB)
AN 358: Thermal Management for FPGAs
AN 357: Error Detection & Recovery Using CRC in Altera FPGA Devices
AN 355: Stratix II Device System Power Considerations
AN 353: SMT Board Assembly Process Recommendations
AN 352: FPGA Peripheral Expansion & FPGA Co-Processing
AN 351: Simulating Nios II Embedded Processor Designs
AN 351 Software Files (6 KB)
AN 350: Upgrading Nios Processor Systems to the Nios II Processor
AN 349: QDR SRAM Controller Reference Design for Stratix & Stratix GX Devices
AN 348: Interfacing DDR SDRAM with Cyclone Devices
AN 346: Using the Nios II Configuration Controller Reference Designs
AN 345: Altera Design Flow for Lattice Semiconductor Users
AN 344: ASI Demonstration
AN 343: OpenCore Evaluation of AMPP Megafunctions
AN 342: Interfacing DDR SDRAM with Stratix & Stratix GX Devices
AN 341: Using the Design Security Feature in Stratix II and Stratix II GX Devices
AN 340: Altera Software Licensing
AN 339: Serial Digital Interface Demonstration for Stratix II GX Devices
AN 336: Using External Series and Parallel Termination with Stratix and Stratix GX Devices
AN 334: ADI Parallel Port SDRAM Controller Reference Design
AN 333: Developing Peripherals for SOPC Builder
Slave Peripheral Design Files (455 KB) 
Streaming Slave 1C20 Design Files (1 MB) 
Streaming Slave 1S10 Design Files (1 MB) 
Streaming Slave 1S10ES Design Files (1 MB) 
Streaming Slave 1S40 Design Files (1 MB)
AN 330: Connecting Altera 3.3-V PCI devices to a 5-V PCI Bus
AN 329: ZBT SRAM Controller Reference Design for Stratix & Stratix GX Devices
AN 328: Interfacing DDR2 SDRAM with Stratix II, Stratix II GX, and Arria GX Devices
ALTMEMPHY Example (604 KB) 
Legacy PHY Example (330 KB)
AN 327: Interfacing DDR SDRAM with Stratix II Devices
AN 326: Interfacing QDRII+ & QDRII with Stratix II, Stratix II GX, Stratix, & Stratix GX Devices
AN 325: Interfacing RLDRAM II with Stratix II, Stratix & Stratix GX Devices
AN 320: OpenCore Plus Evaluation of Megafunctions
AN 317: Turbo Encoder Co-processor Reference Design
AN 315: Guidelines for Designing High-Speed FPGA PCBs
AN 313: Implementing Clock Switchover in Stratix & Stratix GX Devices
Clock Switchover Example Design (233 KB)
AN 311: ASIC-to-FPGA Design Methodology and Guidelines
AN 307: Altera Design Flow for Xilinx Users
an307_DesignExample.zip (4 KB)
AN 306: Implementing Multipliers in FPGA Devices
AN 294: Crosspoint Switch Matrices in Altera MAX Series
Design Example for MAX II and MAX 3000A: 16 x 16 Crosspoint Switch (6 KB) 
Design Example for MAX II and MAX 3000A: Customized Crosspoint Switch (7 KB)
AN 286: Implementing LED Drivers in Altera MAX Series
Design Example for MAX II (3 KB)
AN 283: Simulating Altera Devices with IBIS Models
AN 282: Implementing PLL Reconfiguration in Stratix & Stratix GX Devices
Example 1: Shift Register in LEs (340 KB) 
Example 2: altpll_reconfig Design with the MIF (192 KB) 
Example 3: altpll_reconfig Design (192 KB)
AN 265: Using Altera MAX Series as Microcontroller I/O Expanders
Design Example for MAX II, MAX V, and MAX 3000A (8 KB)
AN 245: Filtering Reference Design Lab
AN 236: Using Source-Synchronous Signaling with DPA in Stratix GX Devices
AN 224: High-Speed Board Layout Guidelines
AN 210: Converting Memory from Asynchronous to Synchronous for Stratix & Stratix GX Designs
AN 132: Implementing Multiprotocol Label Switching with Altera PLDs
AN 115: Using the ClockLock & ClockBoost PLL Features in APEX Devices
AN 114: Designing with High-Density BGA Packages for Altera Devices
AN 111: Embedded Programming Using the 8051 and Jam Byte-Code
AN 109: Using the HP 3070 Tester for In-System Programming
AN 100: In-System Programmability Guidelines
AN 95: In-System Programmability in MAX Devices
AN 71: Guidelines for Handling J-Lead, QFP, BGA, FBGA, and Lidless Devices
AN 49: Implementing CRCCs in Altera Devices
AN 713: DC-Coupling in Stratix V Devices
AN 697: Implementing Audio IP in SDI II on Arria V Development Board
Design Files for AN 697 (3 MB)
AN695: Clock Reconstruction with Low-Cost External DCXO
AN695 Design Files (17 KB)
AN 686:Implementing 9.8G CPRI in Arria V GT and ST FPGAs
AN686 Reference Design (4 MB)
AN 680: Product Security Features for Altera Devices

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