Package and Thermal Resistance

Package information includes the ordering code reference, package acronym, leadframe material, lead finish (plating), JEDEC® outline reference, lead coplanarity, weight, moisture sensitivity level, and other special information. The thermal resistance information includes device pin count, package name, and resistance values.

Stratix Series Arria Series Cyclone Series MAX Series HardCopy Series Serial Configuration Devices
Stratix V Arria 10 Cyclone 10  MAX 10 HardCopy IV EPCQ-L
Stratix IV Arria V Cyclone V MAX V HardCopy III EPCQ
Stratix III Arria II Cyclone IV MAX II   EPCS
    Cyclone III      


For other devices not listed in the table above, please see the Devices Packaging Datasheet.

Search using Package Drawing Search.

For other related packaging technical information, refer to the following literature.

Application Notes

AN752: Guidelines for Handling Altera Wafer Level Chip Scale Package

(This application note provides guidelines for handling Altera’s Wafer Level Chip Scale Package (WLCSP) components.)

AN659: Thermal Management and Mechanical Handling for Lidless Flip Chip Ball-Grid Array
(This application note provides guidance on thermal management and mechanical handling of lidless flip chip ball-grid array (FCBGA) for Altera devices. )
AN 114: Designing with High-Density BGA Packages for Intel Devices 
AN 353: SMT Board Assembly Process Recommendations
AN 71: Guidelines for Handling J-Lead, QFP, BGA, FBGA, and Lidless Devices
White Papers
Challenges in Manufacturing Reliable Lead-Free and RoHS-Compliant Components