Monte Carlo Black-Scholes Asian Options Pricing Design Example

The following example demonstrates an Open Computing Language (OpenCLTM) implementation of an Asian option pricing algorithm. An Asian option is a financial instruction whose price is path dependent. The payoff of such an option is dependent on the average price over a number of sampled points from the start time to the time of maturity. This example specifically considers the pricing of arithmetic Asian options.

Through the use of multiple kernels and Intel's channels vendor extension, this example shows how to efficiently implement a Monte Carlo simulation to price Asian options. At the core of the computation is a kernel implementing the Black-Scholes model. Two other kernels implement a Mersenne Twister random number generator, which is used to supply random numbers to the Black-Scholes kernel using channels as the communication mechanism. Finally, the output from the Black-Scholes kernel is aggregated by another kernel to produce the total payoff value. A detailed explanation can be found in the source code in the design example package.

This example also supports simultaneous execution on multiple OpenCL devices. Each device is dedicated to pricing an Asian option with a different set of parameters, demonstrating scalable parallel offload of many option price calculations.

Performance Scaling with Multiple OpenCL Devices

OpenCL Board One Device Two Devices
BittWare S5-PCIe-HQ D812 Billion Simulations/s24 Billion Simulations/s

Features

  • Channels vendor extension
  • Double-precision floating-point
  • Multiple device execution
  • Multiple kernels, including single work-item kernels

Downloads

The design example provides source code for the OpenCL device (.cl) as well as the host application. For compiling the host application, the Linux package includes a Makefile and the Windows package includes a Microsoft Visual Studio 2010 project.

The following downloads are provided for this example (v17.0 example comping soon):

The use of this design is governed by, and subject to, the terms and conditions of the hardware reference design license agreement.

Software and Hardware Requirements

This design example requires the following tools:

  • Intel® FPGA Software v16.1 or later
  • Intel® FPGA SDK for OpenCL™ v16.1 or later
  • On Linux: GNU Make and gcc
  • On Windows: Microsoft Visual Studio 2010

To download the Intel design tools, visit the OpenCL download page. The requirements for the underlying operating system are the same as those of the Intel FPGA SDK for OpenCL.

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* Product is based on a published Khronos Specification, and has passed the Khronos Conformance Testing Process. Current conformance status can be found at www.khronos.org/conformance.

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These design examples may only be used within Altera Corporation devices and remain the property of Altera. They are being provided on an “as-is” basis and as an accommodation; therefore, all warranties, representations, or guarantees of any kind (whether express, implied, or statutory) including, without limitation, warranties of merchantability, non-infringement, or fitness for a particular purpose, are specifically disclaimed. Altera expressly does not recommend, suggest, or require that these examples be used in combination with any other product not provided by Altera.