Gzip is a widely used compression and decompression method. This design example presents a compression implementation using Intel® FPGA SDK for OpenCL™ that demonstrates:
- Highly competitive performance against CPU, register transfer level (RTL), and ASIC implementations: 2.84 GBps
- Significant productivity boost compared to RTL or ASIC implementations: OpenCL implementation completed in one month
Details about the implementation and results can be found in the paper Gzip on a Chip: High Performance Lossless Data Compression on FPGAs using OpenCL, which was presented as part of the International Workshop on OpenCL 2014.
The design example provides a source code for the OpenCL device (.cl) as well as the host application. For compiling the host application, the Linux* package includes a Makefile and the Windows* package includes a Microsoft* Visual Studio 2010 project.
The use of this design is governed by, and subject to, the terms and conditions of the hardware reference design license agreement.
Software and Hardware Requirements
This design example requires the following tools:
- Intel Quartus® Prime software v17.1 or later
- Intel FPGA SDK for OpenCL™ v17.1 or later
- On Linux: GNU Make and gcc
- On Windows: Microsoft Visual Studio 2010
To download the Intel design tools, visit the OpenCL download page. Only the Linux operating system is supported by this design example.
OpenCL and the OpenCL logo are trademarks of Apple Inc. used by permission by Khronos.
* Product is based on a published Khronos Specification, and has passed the Khronos Conformance Testing Process. Current conformance status can be found at www.khronos.org/conformance.
Figure 1 Performance Comparison
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