- Efficient 1D sliding window buffer
- Single work-item kernel
- Detailed optimization guide (see the Downloads section)
- Third-party benchmark
The design example provides source code for the OpenCL device (.cl) as well as the host application. For compiling the host application, the Linux package includes a Makefile and the Windows package includes a Microsoft Visual Studio 2010 project.
The following downloads are provided for this example:
The use of this design is governed by, and subject to, the terms and conditions of the hardware reference design license agreement.
Software and Hardware Requirements
This design example requires the following tools:
- Intel® FPGA Software v17.0 or later
- Intel® FPGA SDK for OpenCL™ v17.0 or later
- On Linux: GNU Make and gcc
- On Windows: Microsoft Visual Studio 2010
To download the Intel design tools, visit the OpenCL download page. The requirements for the underlying operating system are the same as those of the Intel FPGA SDK for OpenCL.
OpenCL and the OpenCL logo are trademarks of Apple Inc. used by permission by Khronos.
* Product is based on a published Khronos Specification, and has passed the Khronos Conformance Testing Process. Current conformance status can be found at www.khronos.org/conformance.
Design Examples Disclaimer
These design examples may only be used within Altera Corporation devices and remain the property of Altera. They are being provided on an “as-is” basis and as an accommodation; therefore, all warranties, representations, or guarantees of any kind (whether express, implied, or statutory) including, without limitation, warranties of merchantability, non-infringement, or fitness for a particular purpose, are specifically disclaimed. Altera expressly does not recommend, suggest, or require that these examples be used in combination with any other product not provided by Altera.