For more information about Qsys refer to the Qsys System Integration Tool Support page.
The following examples show how you can use the Qsys system integration tool and create Qsys components in the Quartus® II software:
- Qsys tutorial design example - This example includes the system components to design a hierarchical memory tester system with Avalon® Memory-Mapped (Avalon-MM) interfaces by following the procedures in the Qsys System DesignTutorial (PDF).
- Demo AXITM-3 memory - This is an example of a demonstration memory component that uses an AXI-3 memory-mapped interface along with Avalon interfaces for control registers and streaming data. This example is referenced in the Creating Qsys Designer Components (PDF) and Component Interface Tcl Reference (PDF) chapters of the Quartus II handbook.
- AXI bus functional model (BFM) simulation example - This example instantiates the Hard Processor System (HPS) along with an AXI-3 slave on-chip memory component in a Qsys system, and demonstrates how to simulate the design.
- Other Qsys-compliant design examples - Refer to the Design Examples pages and sort in the Qsys Compliant column to find other design examples that use the Qsys system integration tool to illustrate specific technology areas like Embedded Processors or External Memory Interfaces.
Design Examples Disclaimer
These design examples may only be used within Altera Corporation devices and remain the property of Altera. They are being provided on an “as-is” basis and as an accommodation; therefore, all warranties, representations, or guarantees of any kind (whether express, implied, or statutory) including, without limitation, warranties of merchantability, non-infringement, or fitness for a particular purpose, are specifically disclaimed. Altera expressly does not recommend, suggest, or require that these examples be used in combination with any other product not provided by Altera.