This design example demonstrates an AMBA® AXITM-3 slave interface on a simple Verilog custom memory component for Qsys systems. You can use this example as a basis for your own custom AXI slave interfaces. The component also includes an optional Avalon® Streaming (Avalon-ST) interface and Avalon Memory-Mapped (Avalon-MM) interface, demonstrating how multiple interface standards can be used in one component.
The Quartus® II Handbook uses this example to illustrate the process of packaging an intellectual property (IP) component with the Component Editor and custom hardware Tcl commands. You can use the HDL files in this example to help you learn how to use the Component Editor to create your own simple hardware Tcl (_hw.tcl) file, as described in the Creating Qsys Components (PDF) chapter. You can also refer to the included _hw.tcl file to see advanced uses of hardware Tcl commands, including derived parameters, a validation callback, and an elaboration callback to customize the parameterization UI in Qsys and present interfaces as optional. For details on hardware Tcl commands, refer to the Component Interface Tcl Reference (PDF) chapter.
For more information on using Qsys to create a system that includes custom components, refer to the Creating a System with Qsys (PDF) chapter in the Quartus II Handbook.
Using This Design Example
Download the file demo_axi3_memory.zip and extract the contents. This design example requires the Altera® Complete Design Suite (ACDS) v13.0 or later.
The ZIP file includes the following IP component files in the /ip subdirectory:
- The design files demo_axi_memory.sv and single_clock_ram.sv
- The custom hardware Tcl file demo_axi_memory_hw.tcl to package the component for Qsys
- A SystemVerilog package file used to generate messages in simulation output, /verification_lib/verbosity_pkg.sv (which can also be found in the Quartus II software installation directory as /ip/altera/sopc_builder_ip/verification/lib/verbosity_pkg.sv)
To use this component in your own Qsys system, copy the /ip subdirectory from the extracted ZIP file to your Quartus II project directory. When you create or open a Qsys system in the project, Qsys detects the IP component in the /ip subdirectory and adds the component to the list in the Project section of the Library, under the category Memories and Memory Controllers/On-Chip.
The ZIP file also contains the following files to simulate the standalone component, in the /ip/simulation subdirectory:
- A testbench file tb_mem.sv
- A script run_sim.tcl to perform a simulation in Mentor Graphics® ModelSim® with mem.do file to display waveforms showing the component operation
To run a simulation in ModelSim, set your working directory to the /ip/simulation subdirectory from the extracted ZIP file. Type source run_sim.tcl.
In addition, the ZIP file contains the following Quartus II software files:
- A simple test Qsys system test.qsys to illustrate instantiation of the component in a Qsys system
- A dummy Quartus II software project file so that you can optionally generate and compile the test Qsys system: test.qpf, test.qsf, test.sdc
To view the component instantiated as part of the test Qsys system, open the test.qpf project file in the Quartus II software, and open the test.qsys file in Qsys. Double-click on the component in the Name or Description column of the System Contents tab (or right-click on the component and choose Edit) to view the parameter editor.
The use of this design is governed by, and subject to, the terms and conditions of the Altera hardware reference design license agreement.
The example Qsys component includes the following interfaces:
AXI-3 Slave Interface
The AXI slave interface is a memory-mapped interface to an on-chip memory block. This interface is intended to be controlled by an AXI or Avalon-MM master interface, which can write to and read from the memory block. Parameters specify the AXI ID signal widths, the slave address width, and the data width.
When you instantiate this component in Qsys, you can choose to enable or disable the optional Avalon-ST source interface. This interface was inspired by telephony applications, in which tones (DTMF, busy, dial tone, ringback, etc.) are all stored as repeating streams of bytes that can be switched as needed to a particular port. The Avalon-ST port provides one such stream, which is defined by a start address, a stop address, and the data stored in the RAM between those two addresses, inclusively. The words are output in order from the start address to the stop address; each word outputs MSB first. This demo version assumes the stop address to be larger than the start address.
For example, consider the following memory contents:
start address: 0xbeef_0742
stop address: 0xb0de_13ef
The resulting byte stream would be: be-ef-07-42-da-ce-32-f7-b0-de-13-ef-be-ef-07 …
Avalon-MM CSR Interface
The Avalon-MM interface is a simple control and status register (CSR) interface, to control the streaming port described above. This interface is required only when the Avalon-ST interface is enabled, and is disabled when the Avalon-ST interface is disabled. Parameters specify the Avalon slave address width and data width.
The control registers lie in an address range separate from the address range of the memory, and their base address may be assigned anywhere convenient in the system memory map. The following table lists the purpose for each control register:
|Base_addr + 2||Run |
|Base_addr + 1||Stop address [AV_DATA_W-1:0]|
|Base_addr + 0||Start address [AV_DATA_W-1:0]|
Qsys Parameter Editor
The following screenshot shows the parameter editor UI for the Demo AXI Memory component in Qsys.
Design Examples Disclaimer
These design examples may only be used within Altera Corporation devices and remain the property of Altera. They are being provided on an “as-is” basis and as an accommodation; therefore, all warranties, representations, or guarantees of any kind (whether express, implied, or statutory) including, without limitation, warranties of merchantability, non-infringement, or fitness for a particular purpose, are specifically disclaimed. Altera expressly does not recommend, suggest, or require that these examples be used in combination with any other product not provided by Altera.