BFM Simulation Example: HPS AXI* Bridge Interface to FPGA Core

The Hard Processor System (HPS) in Intel SoC devices has a HPS-to-FPGA AXI* Bridge (h2f) interface for communicating with memories and peripherals in the FPGA core. This example instantiates an HPS along with an AXI slave on-chip memory component in a Platform Designer (formerly Qsys), and demonstrates how to simulate the design. The testbench system uses the Mentor Graphics* Master bus functional model (BFM) to model the HPS AXI Bridge interface communicating with the FPGA core logic.

Using This Design Example

Download the file HPS_h2f_axi_sim.zip and extract its contents. This design example requires the Intel Quartus® Prime software v13.1 or later.

The ZIP file includes the following IP directory and simulation directories to run the simulation and view the results:

  • The top-level Qsys system called HPS_h2f_axi_sim.qsys
  • The AXI Slave memory files in the ip/ directory
  • The simulation files under the HPS_h2f_axi_simulation_example/ directory as follows:
    • testbench/mentor/ - Contains setup files for running the simulation using ModelSim. The main script file is run_sim.tcl.
    • testbench/HPS_h2f_axi_sim_tb/simulation/ - Contains the top-level testbench and test program. The top-level testbench file is HPS_h2f_axi_sim_tb.v and the test program is master_test_program.sv.
    • testbench/HPS_h2f_axi_sim_tb/simulation/submodules/ - Sub-directory contains the Verilog files needed to compile the design.

The top-level testbench instantiates the HPS simulation model, a clock source, a reset source, and the master test program. The test program sends commands from the HPS BFM model using the h2f AXI Bridge interface to the AXI Slave memory. The test program performs a directed test to initiate four writes followed by four reads followed by two write data bursts and two read data bursts. Finally, the test program verifies that the data read from the AXI Slave memory matches the data written.

You can use the included simulation script to run a simulation with the Mentor Graphics ModelSim*-Intel FPGA Edition simulator. To run the simulation you need to have an installed Mentor Graphics AXI Verification IP Suite license, which is included with the Intel Quartus Prime Standard and Pro Edition license. To launch the ModelSim -Intel FPGA Edition software, use the command shown below with the -mvchome path pointing to the correct installation directory:
vsim -mvchome $QUARTUS_ROOTDIR/../ip/altera/mentor_vip_ae/common

Launch the ModelSim-Intel FPGA Edition software from the HPS_h2f_axi_simulation_example/testbench/mentor/ directory. You can then run the simulation and view the waveform by executing the run_sim.tcl script.

The test program in master_test_program.sv is based on the example provided in the Mentor Graphics AXI Verification IP Suite (Intel FPGA Edition) that is described in more detail in chapter 6 of the Mentor VIP Intel FPGA Edition AMBA, AXI3, and AXI4 User Guide (PDF).

The user guide also contains an example with back-to-back Master and Slave BFMs in Chapter 12, and instructions to run the simulation using ModelSim-Intel FPGA, Questa, and VCS simulators.

Design Examples Disclaimer

These design examples may only be used within Intel Corporation devices and remain the property of Intel. They are being provided on an “as-is” basis and as an accommodation; therefore, all warranties, representations, or guarantees of any kind (whether express, implied, or statutory) including, without limitation, warranties of merchantability, non-infringement, or fitness for a particular purpose, are specifically disclaimed. Intel expressly does not recommend, suggest, or require that these examples be used in combination with any other product not provided by Intel.